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4–42 Chapter 4: Functional Description
Logical Layer Interfaces
RapidIO II MegaCore Function August 2014 Altera Corporation
User Guide
User Receiving MAINTENANCE Read Requests and Sending Responses
Table 4–21 lists the Maintenance Avalon-MM interface usage example this section
describes.
CRF
0
prio[1:0]
The IP core assigns to this field the value programmed in the
PRIORITY
field of
the
Tx Maintenance Mapping Window n Control
register (Table 6–44 on
page 6–36) for the matching address translation window
n
. Refer to “Defining
the Maintenance Address Translation Windows” on page 4–34 for matching
details.
tt[1:0]
2'b01 The value of 1 indicates 16-bit device IDs.
ftype[3:0]
4'b1000 The value of 8 indicates a Maintenance Class packet.
destinationID[15:0]
The IP core assigns to this field the value {
LARGE_DESTINATION_ID,
DESTINATION_ID}
, based on the values programmed in the
LARGE_DESTINATION_ID
and
DESTINATION_ID
fields of the
Tx
Maintenance Mapping Window n Control
register (Table 6–44 on
page 6–36) for the matching address translation window
n
. Refer to “Defining
the Maintenance Address Translation Windows” on page 4–34 for matching
details.
sourceID[15:0]
The IP core assigns to this field the value programmed in the
Large_base_deviceID
field of the
Base Device ID
register (offset 0x60).
ttype[3:0]
4’b0000 The value of 0 indicates a
MAINTENANCE
read request.
rdsize[3:0]
4'b1000
The
size
and
wdptr
values encode the maximum size of the payload field. In
MAINTENANCE
transactions, the value of
wrsize
is always 4’b1000, which
decodes to a value of 4 bytes. For encoding details, refer to Table 4-4 in Part 1:
Input/Output Logical Specification of the RapidIO Interconnect Specification,
Revision 2.2.
srcTID[7:0]
The RapidIO II IP core generates the source transaction ID value internally to
track the transaction response. The value depends on the current state of the
RapidIO II IP core when it prepares the RapidIO packet.
config_offset[20:0]
Depends on the values programmed in the
Tx Maintenance Address
Translation Window
registers, as defined in Table 6–41 through Table 6–44.
Refer to “Defining the Maintenance Address Translation Windows” on
page 4–34 for the matching and conversion calculations.
wdptr
The IP core assigns to this field the negation of
mnt_s_address[0]
.
hop_count
The IP core assigns to this field the value programmed in the
HOP_COUNT
field
of the
Tx Maintenance Mapping Window n Control
register (Table 6–44
on page 6–36) for the matching address translation window
n
. Refer to
“Defining the Maintenance Address Translation Windows” on page 4–34 for
matching details.
Table 4–20. Maintenance Read Request Transmit Example: RapidIO Packet Fields (Part 2 of 2)
Field Value Comment
Table 4–21. Maintenance Interface Usage Example: Receiving MAINTENANCE Read Request and
Sending Response
User Operation Device ID Width
Payload Size
(Bytes)
Receive
MAINTENANCE
read request 16 0
Send
MAINTENANCE
read response 16 32
- User Guide 1
- RapidIO II MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbench 6
- 1. About The RapidIO II 9
- MegaCore Function 9
- Releases 10
- RapidIO II IP Core Features 10
- Features 11
- Device Family Support 12
- IP Core Verification 13
- Hardware Testing 14
- Interoperability Testing 14
- Note to Table 1–3: 16
- Notes to Table 1–4: 16
- Installation and Licensing 17
- 2. Getting Started 19
- Simulating IP Cores 22
- Transceiver Settings 26
- External Transceiver PLL 26
- 3. Parameter Settings 31
- Note to Table 3–1: 32
- Enable 16-Bit Device ID Width 33
- Logical Layer Settings 34
- Capability Registers Settings 35
- Device ID 36
- Vendor ID 36
- Revision ID 36
- Assembly ID 36
- Assembly Information CAR 37
- Enable Flow Control Support 38
- Enable Switch Support 38
- Number of Ports 38
- Port Number 39
- Maximum PDU 39
- Destination Operations CAR 40
- Port General Control CSR 40
- Port 0 Control CSR 41
- Lane n Status 0 CSR 41
- Extended Features Pointer CSR 41
- 4. Functional Description 43
- Note to Table 4–2: 44
- Clocking and Reset Structure 45
- Notes to Table 4–3: 46
- RapidIO II 47
- Transactions 55
- Notes to Table 4–6: 57
- Notes to Table 4–7: 59
- Note to Table 4–8: 59
- Note to Figure 4–9: 66
- Note to Table 4–10: 70
- Notes to Table 4–11: 71
- Table 6–60 on page 6–40 72
- Note to Table 4–12: 73
- Maintenance Module 74
- Maintenance Interface Signals 75
- Doorbell Module Block Diagram 86
- Preserving Transaction Order 87
- Doorbell Module Signals 88
- Generating a Doorbell Message 88
- Receiving a Doorbell Message 89
- Transaction ID Ranges 90
- Notes to Table 4–24: 92
- Note to Table 4–26: 94
- Note to Table 4–27: 95
- field 97
- User Receiving Write Request 100
- Logical Layer Interfaces 101
- Transport Layer 112
- Receiver 113
- Transmitter 114
- Physical Layer 115
- Physical Layer Interfaces 116
- Low-level Interface Receiver 116
- CRC Checking and Removal 117
- Protocol Violations 119
- Fatal Errors 119
- Maintenance Avalon-MM Slave 120
- Maintenance Avalon-MM Master 121
- Port-Write Reception Module 122
- Input/Output Avalon-MM Slave 122
- Input/Output Avalon-MM Master 123
- 5. Signals 125
- Physical Layer Signals 126
- Low Latency Signals 127
- Multicast Event Signals 128
- Chapter 5: Signals 5–5 129
- Note to Table 5–7: 130
- Chapter 5: Signals 5–7 131
- 5–8 Chapter 5: Signals 132
- Register-Related Signals 133
- Avalon-MM Interface Signals 133
- Note to Table 5–12: 134
- Chapter 5: Signals 5–11 135
- Note to Table 5–15: 136
- Error Reporting Signals 137
- 5–14 Chapter 5: Signals 138
- 6. Software Interface 139
- Memory Map 140
- Physical Layer Registers 144
- Note to Table 6–9: 147
- Note to Table 6–14: 154
- Note to Table 6–15: 158
- Note to Table 6–17: 160
- Note to Table 6–22: 164
- Note to Table 6–23: 164
- Note to Table 6–24: 165
- Note to Table 6–25: 165
- Note to Table 6–26: 166
- Note to Table 6–27: 167
- Notes to Table 6–28: 168
- Notes to Table 6–29: 169
- Note to Table 6–30: 169
- Note to Table 6–31: 169
- Notes to Table 6–32: 170
- Note to Table 6–34: 171
- Note to Table 6–35: 171
- Note to Table 6–36: 172
- Note to Table 6–37: 172
- Transmit Port-Write Registers 174
- Receive Port-Write Registers 175
- Note to Table 6–59: 178
- Error Management Registers 180
- Note to Table 6–66: 181
- Notes to Table 6–67: 183
- Notes to Table 6–70: 185
- Notes to Table 6–71: 185
- Doorbell Message Registers 191
- Note to Table 6–89: 193
- 7. Testbench 195
- 7–2 Chapter 7: Testbench 196
- Testbench Overview 196
- Testbench Sequence 197
- 7–4 Chapter 7: Testbench 198
- Chapter 7: Testbench 7–5 199
- SWRITE Transactions 200
- NREAD Transactions 200
- NWRITE_R Transactions 201
- NWRITE Transactions 202
- Doorbell Transactions 202
- Port-Write Transactions 203
- Testbench Completion 204
- Chapter 7: Testbench 7–11 205
- 7–12 Chapter 7: Testbench 206
- A. Initialization Sequence 207
- MegaCore Function v12.1 209
- Additional Information 213
- Info–2 Additional Information 214
- Document Revision History 214
- Additional Information Info–3 215
- Info–4 Additional Information 216
- Note to Table: 217
- Info–6 Additional Information 218
- Typographic Conventions 218
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