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Chapter 4: Functional Description 4–59
Logical Layer Interfaces
August 2014 Altera Corporation RapidIO II MegaCore Function
User Guide
Figure 4–22 shows the behavior of the signals on the Avalon-ST pass-through
interface for this example transaction.
In the first clock cycle of the example, user logic asserts
gen_rx_hd_ready
and
gen_rx_pd_ready
, and the IP core asserts
gen_rx_hd_valid
and
gen_rx_pd_valid
,
indicating it is providing valid data on
gen_rx_hd_data
and
gen_rx_pd_data
,
respectively. The assertion of both the ready signal and the valid signal on each of the
header and payload-data Avalon-ST interfaces makes the current cycle an Avalon-ST
ready cycle for both header and data.
The IP core asserts
gen_rx_pd_startofpacket
to indicate the current cycle is the first
valid data cycle of the packet. In this clock cycle, the IP core also makes the header
and the first 128 bits of payload data available on
gen_rx_hd_data
and
gen_rx_pd_data
, respectively. The 40-byte payload requires 3 clock cycles. In the third
clock cycle of data transfer, the IP core asserts
gen_rx_pd_endofpacket
to indicate this
is the final clock cycle of data transfer, and specifies in
gen_rx_pd_empty
that in the
current clock cycle, the four least significant two-byte segments (the least significant
eight bytes) of
gen_rx_pd_data
are not valid. Following the clock cycles in which valid
data is available on
gen_rx_pd_data
, the IP core deasserts
gen_rx_pd_valid
.
Table 4–35 lists the header fields in this example.
Figure 4–22. Avalon-ST Pass-Through Interface NWRITE Receive Example
clk
gen_rx_hd_ready
gen_rx_hd_valid
000102030405060708090A0B0C0D0E0F 101112131415161718191A1B1C1D1E1F 20212223242526270000000000000000
4
0A00500DD00AA4C00FEDCBA940000
gen_rx_hd_data[114:0]
gen_rx_pd_ready
gen_rx_pd_valid
gen_rx_pd_startofpacket
gen_rx_pd_endofpacket
gen_rx_pd_data[127:0]
gen_rx_pd_empty[2:0]
Table 4–35. NWRITE Request Receive Example: RapidIO Header Fields in gen_rx_hd_data Bus (Part 1 of 2)
Field
gen_rx_hd_data
Bits
Value Comment
pd_size[8:0]
[114:106] 9’h028 Payload data size is 0x28 (decimal 40).
VC
[105] 0 The RapidIO II IP core supports only VC0.
CRF
[104] 0
prio[1:0]
[103:102] 2’b00
tt[1:0]
[101:100] 2’b00 Indicates 8-bit device IDs.
ftype[3:0]
[99:96] 4’b0101 The value of 5 indicates a Write Class packet.
destinationID[15:0]
[95:80] 16’h00DD
For variations with an 8-bit device ID, bits [95:88] (bits
[15:8] of the destinationID) are set to 8’h00.
- User Guide 1
- RapidIO II MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbench 6
- 1. About The RapidIO II 9
- MegaCore Function 9
- Releases 10
- RapidIO II IP Core Features 10
- Features 11
- Device Family Support 12
- IP Core Verification 13
- Hardware Testing 14
- Interoperability Testing 14
- Note to Table 1–3: 16
- Notes to Table 1–4: 16
- Installation and Licensing 17
- 2. Getting Started 19
- Simulating IP Cores 22
- Transceiver Settings 26
- External Transceiver PLL 26
- 3. Parameter Settings 31
- Note to Table 3–1: 32
- Enable 16-Bit Device ID Width 33
- Logical Layer Settings 34
- Capability Registers Settings 35
- Device ID 36
- Vendor ID 36
- Revision ID 36
- Assembly ID 36
- Assembly Information CAR 37
- Enable Flow Control Support 38
- Enable Switch Support 38
- Number of Ports 38
- Port Number 39
- Maximum PDU 39
- Destination Operations CAR 40
- Port General Control CSR 40
- Port 0 Control CSR 41
- Lane n Status 0 CSR 41
- Extended Features Pointer CSR 41
- 4. Functional Description 43
- Note to Table 4–2: 44
- Clocking and Reset Structure 45
- Notes to Table 4–3: 46
- RapidIO II 47
- Transactions 55
- Notes to Table 4–6: 57
- Notes to Table 4–7: 59
- Note to Table 4–8: 59
- Note to Figure 4–9: 66
- Note to Table 4–10: 70
- Notes to Table 4–11: 71
- Table 6–60 on page 6–40 72
- Note to Table 4–12: 73
- Maintenance Module 74
- Maintenance Interface Signals 75
- Doorbell Module Block Diagram 86
- Preserving Transaction Order 87
- Doorbell Module Signals 88
- Generating a Doorbell Message 88
- Receiving a Doorbell Message 89
- Transaction ID Ranges 90
- Notes to Table 4–24: 92
- Note to Table 4–26: 94
- Note to Table 4–27: 95
- field 97
- User Receiving Write Request 100
- Logical Layer Interfaces 101
- Transport Layer 112
- Receiver 113
- Transmitter 114
- Physical Layer 115
- Physical Layer Interfaces 116
- Low-level Interface Receiver 116
- CRC Checking and Removal 117
- Protocol Violations 119
- Fatal Errors 119
- Maintenance Avalon-MM Slave 120
- Maintenance Avalon-MM Master 121
- Port-Write Reception Module 122
- Input/Output Avalon-MM Slave 122
- Input/Output Avalon-MM Master 123
- 5. Signals 125
- Physical Layer Signals 126
- Low Latency Signals 127
- Multicast Event Signals 128
- Chapter 5: Signals 5–5 129
- Note to Table 5–7: 130
- Chapter 5: Signals 5–7 131
- 5–8 Chapter 5: Signals 132
- Register-Related Signals 133
- Avalon-MM Interface Signals 133
- Note to Table 5–12: 134
- Chapter 5: Signals 5–11 135
- Note to Table 5–15: 136
- Error Reporting Signals 137
- 5–14 Chapter 5: Signals 138
- 6. Software Interface 139
- Memory Map 140
- Physical Layer Registers 144
- Note to Table 6–9: 147
- Note to Table 6–14: 154
- Note to Table 6–15: 158
- Note to Table 6–17: 160
- Note to Table 6–22: 164
- Note to Table 6–23: 164
- Note to Table 6–24: 165
- Note to Table 6–25: 165
- Note to Table 6–26: 166
- Note to Table 6–27: 167
- Notes to Table 6–28: 168
- Notes to Table 6–29: 169
- Note to Table 6–30: 169
- Note to Table 6–31: 169
- Notes to Table 6–32: 170
- Note to Table 6–34: 171
- Note to Table 6–35: 171
- Note to Table 6–36: 172
- Note to Table 6–37: 172
- Transmit Port-Write Registers 174
- Receive Port-Write Registers 175
- Note to Table 6–59: 178
- Error Management Registers 180
- Note to Table 6–66: 181
- Notes to Table 6–67: 183
- Notes to Table 6–70: 185
- Notes to Table 6–71: 185
- Doorbell Message Registers 191
- Note to Table 6–89: 193
- 7. Testbench 195
- 7–2 Chapter 7: Testbench 196
- Testbench Overview 196
- Testbench Sequence 197
- 7–4 Chapter 7: Testbench 198
- Chapter 7: Testbench 7–5 199
- SWRITE Transactions 200
- NREAD Transactions 200
- NWRITE_R Transactions 201
- NWRITE Transactions 202
- Doorbell Transactions 202
- Port-Write Transactions 203
- Testbench Completion 204
- Chapter 7: Testbench 7–11 205
- 7–12 Chapter 7: Testbench 206
- A. Initialization Sequence 207
- MegaCore Function v12.1 209
- Additional Information 213
- Info–2 Additional Information 214
- Document Revision History 214
- Additional Information Info–3 215
- Info–4 Additional Information 216
- Note to Table: 217
- Info–6 Additional Information 218
- Typographic Conventions 218
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