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Flash Access Mode

Configura‐

tion Data

Option

Flash Data

Width (bits)

DCLK Ratio = 1, 2, 4, or 8

(9)

FPP Mode PS Mode

• For Normal Mode and Burst Mode:

access

= T

access

clk

Total Clock Cycles (from nRESET asserted high to N bytes of data clocked out)

= C

overhead

+ max(C

flash

, C

cfg

)*N

Total Configuration Time = Total Clock Cycle/ PFL Input Clock

• For Page Mode

access

=[(T

access

clk

+1) + (T

page_access

clk

*15)]/16

Total Clock Cycles (from nRESET asserted high to N bytes of data clocked out)

= C

overhead

+ max (C

flash

, C

cfg

)*N

Total Configuration Time = Total Clock Cycle/ PFL Input Clock

• For FPP (×8)

Total Clock Cycles (from nRESET asserted high to N bytes of data clocked out)

flash

remains the same

• For FPP (×16)

Total Clock Cycles (from nRESET asserted high to N word of data clocked out)

flash

= C

flash

× 2 (×2 of C

flash

from FPP ×8)

• For FPP (×32)

Total Clock Cycles (from nRESET asserted high to N double word of data clocked out)

flash

= C

flash

× 4 (×4 of C

flash

from FPP ×8)

Configuration Time Calculation Examples

The following are the configuration time calculation examples for normal mode, page mode, and burst

mode:

Note:

Any reference to the core clock speed of 100 MHz is only an example of the configuration time

calculation and not a recommendation of the actual clock.

(9)

Ratio between input clock and DCLK output clock. For more information, see related information

(10)

Spansion page mode support is only available in the Quartus II software versions 8.0 onwards.

UG-01082

2015.01.23

Specifications

Parallel Flash Loader IP Core User Guide

Altera Corporation

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