Altera Video and Image Processing Suite Manuale Utente Scaricare il pdf (Pagina 68)

• For Clocked Video Output IP Core, the following steps reconfigure mode 1:

1. Write 0 to the Mode1 Valid register.

2. Write to the Mode 1 configuration registers.

3. Write 1 to the Mode1 Valid register. The mode is now valid and can be selected.

• For Clocked Video Output II IP Core, the following steps reconfigure mode 1:

1. Write 1 to the Bank Select register.

2. Write 0 to the Mode N Valid configuration register.

3. Write to the Mode N configuration registers, the Clocked Video Input II IP Core mirrors these

writes internally to the selected bank.

4. Write 1 to the Mode N Valid register. The mode is now valid and can be selected.

You can configure a currently-selected mode in this way without affecting the video output of the CVO IP

cores.

If there are multiple modes that match the resolution, the function selects the lowest mode. For example,

the function selects Mode1 over Mode2 if both modes match. To allow the function to select Mode2,

invalidate Mode1 by writing a 0 to its mode valid register. Invalidating a mode does not clear its configu‐

ration.

Interrupts

The CVO IP cores produce a single interrupt line.

This interrupt line is the OR of the following internal interrupts:

• Status update interrupt—Triggers when the Video Mode Match register is updated by a new video

mode being selected.

• Locked interrupt—Triggers when the outgoing video SOF is aligned to the incoming SOF.

Both interrupts can be independently enabled using bits [2:1] of the Control register. Their values can be

read using bits [2:1] of the Interrupt register. Writing 1 to either of these bits clears the respective

interrupt.

Generator Lock

Generator lock (Genlock) is the technique for locking the timing of video outputs to a reference source.

Sources that are locked to the same reference can be switched between cleanly, on a frame boundary.

You can configure the IP cores to output, using vcoclk_div for CVO IP cores and refclk_div for CVI

IP cores. With the exception of Clocked Video Input II IP core, these signals are divided down versions of

vid_clk (vcoclk) and vid_clk (refclk) aligned to the start of frame (SOF). By setting the divided down

value to be the length in samples of a video line, you can configure these signals to produce a horizontal

reference.

For CVI IP cores, the phase-locked loop (PLL) can align its output clock to this horizontal reference. By

tracking changes in refclk_div, the PLL can then ensure that its output clock is locked to the incoming

video clock.

Note:

For Clocked Video Input II IP core, the refclk_div signal is a pulse on the rising edge of the H

sync which a PLL can align its output clock to.

UG-VIPSUITE

2015.05.04

Interrupts

4-9

Clocked Video Interface IP Cores

Altera Corporation

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Altera Video and Image Processing Suite Manuale Utente Pagina 68

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