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Altera Corporation User Guide Version 11.1 3–1

October 2011

3. Functional Description

This chapter contains detailed information on the PCI Compiler and the

PCI MegaCore functions, including the following:

■ “Functional Overview”

■ “PCI Bus Signals”

■ “PCI Bus Commands”

■ “Configuration Registers”

■ “Target Mode Operation”

■ “Master Mode Operation”

■ “Host Bridge Operation”

■ “64-Bit Addressing, Dual Address Cycle (DAC)”

Functional

Overview

This section provides a general overview of pci_mt64, pci_mt32,

pci_t64, and pci_t32 functionality. It describes the operation and

assertion of master and target signals.

Figures 3–1 through 3–4 show the block diagrams for the pci_mt64,

pci_mt32, pci_t64, and pci_t32 functions, respectively. The

functions consist of several blocks:

■ PCI bus configuration register space—implements all configuration

registers required by the PCI Local Bus Specification, Revision 3.0

■ Parity checking and generation—responsible for parity checking and

generation, as well as assertion of parity error signals and required

status register bits

■ Target interface control logic—controls the operation of the

corresponding PCI MegaCore function on the PCI bus in target mode

■ Master interface control logic—controls the PCI bus operation of the

corresponding PCI MegaCore function in master mode (pci_mt64

and pci_mt32 MegaCore functions only)

■ Local target control—controls local-side interface operation in target

mode

■ Local master control—controls the local side interface operation in

master mode (pci_mt64 and pci_mt32 MegaCore functions only)

■ Local address/data/command/byte enables—multiplexes and registers all

address, data, command, and byte-enable signals to the local side

interface.

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Altera PCI Compiler Manuale Utente Pagina 75