Altera Reed-Solomon II MegaCore Function Manuale Utente

Reed-Solomon II IP Core User GuideSubscribeSend FeedbackUG-010902015.05.01101 Innovation DriveSan Jose, CA 95134www.altera.com

Figure 2-2: Quartus II IP CatalogSearch for installed IP coresDouble-click to customize, right-click for detailed informationShow IP only for target d

• Optionally select preset parameter values if provided for your IP core. Presets specify initialparameter values for specific applications.• Specify

Figure 2-4: IP Core Generated Files<your_testbench>_tb.csv<your_testbench>_tb.spd<your_ip>.cmp - VHDL component declaration file<

File Name Description<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file thatcontains local generic and port definitions that

File Name Description<my_ip>.svdAllows HPS System Debug tools to view the register maps ofperipherals connected to HPS within a Qsys system.Duri

Figure 2-5: Simulation in Quartus II Design FlowPost-fit timing simulation netlist Post-fit timing simulation (3)Post-fit functional simulation net

Related InformationUsing MegaCore Functions chapter in the DSP Builder Handbook.UG-010902015.05.01DSP Builder Design Flow2-9Reed-Solomon II IP Core Ge

Reed-Solomon II IP Core Functional Description32015.05.01UG-01090SubscribeSend FeedbackThis topic describes the IP core’s architecture, interfaces, an

Figure 3-2: Encoder Timing—One ChannelShows the timing diagram of the RS II encoder with one channel.clk_clkreset_reset_nin_validin_startofpacketin_en

Figure 3-3: Codeword Decoding1 238Decoded Codeword239... 237240...255RS II DecoderEncoded Codeword plus noise...The received encoded codeword may d

ContentsAbout the Reed-Solomon II IP Core...1-1Altera DSP IP Core Features...

The codeword starts when you assert the in_valid signal and the in_startofpacket signal.The decoderaccepts the data at in_data as valid data. The code

Figure 3-6: Encoder Timing—Two ChannelsFor a two-channel codeword, the encoder asserts the in_startofpacket and in_endofpacket signals fortwo consecut

Parameter Legal Values Default Value DescriptionNumber of bits persymbol3 to 12 8 Specifies the number of bits per symbol(M).Number of symbolsper code

Parameter Legal Values Default Value DescriptionError bits countformatFull or split Full Specifies full or split count:• With full count the decoder j

Table 3-3: Clock and Reset SignalsName Avalon-ST Type Direction Descriptionclk_clk clk Input The main system clock. The whole IP core operateson the r

Name Avalon-ST Type Direction Descriptionin_error error Input Error signal. Specifies if the input data symbol is anerror and whether the decoder can

Name Avalon-ST Type Direction Descriptionstatus_num_error_symbolconduit Output Number of error symbols in acodeword. This signal is validwhen the IP c

Document Revision History42015.05.01UG-01090SubscribeSend FeedbackReed-Solomon II IP Core User Guide revision history.Date Version Changes2015.05.01 1

Date Version ChangesNovember 2013 13.1• Updated performance data• Added erasures-supportingdecoder• Added status signals toparameters description• Add

Date Version ChangesMay 2011 2.0• Updated About ThisMegaCore Function with newdevice family support.• Updated Functional Descrip‐tion with new status

About the Reed-Solomon II IP Core12015.05.01UG-01090SubscribeSend FeedbackAltera DSP IP Core Features• Avalon® Streaming (Avalon-ST) interfaces• DSP B

Altera® offers the following device support levels for Altera IP cores:• Preliminary support—Altera verifies the IP core with preliminary timing model

Item DescriptionProduct ID 00E5 (Encoder/Decoder)Vendor ID 6AF7Altera verifies that the current version of the Quartus II software compiles the previo

DeviceParametersALMMemory RegistersfMAX(MHz)Type CheckSymbolsBits PerSymbolBits PerCheckSymbolM10K M20K Primary SecondaryArria V Standardencoder16 8 2

DeviceParametersALMMemory RegistersfMAX(MHz)Type CheckSymbolsBits PerSymbolBits PerCheckSymbolM10K M20K Primary SecondaryStratix V Erasuresdecoder16 8

Reed-Solomon II IP Core Getting Started22015.05.01UG-01090SubscribeSend FeedbackInstalling and Licensing IP CoresThe Altera IP Library provides many u

OpenCore Plus evaluation supports the following two operation modes:• Untethered—run the design containing the licensed IP for a limited time.• Tether