Altera PCI Compiler Manuale Utente Scaricare il pdf (Pagina 137)

Altera Corporation User Guide Version 11.1 3–63

October 2011

Functional Description

Target Write Transactions

This section describes the behavior of the PCI MegaCore functions in the

following types of target write transactions:

■ Memory write

■ I/O write

■ Configuration write

Memory Write Transactions

The PCI MegaCore functions support the following types of matched bus

width and mismatched bus width memory write transactions in target

mode:

■ Single-cycle memory write

■ Burst memory write

■ Mismatched bus width memory write

1 Mismatched bus-width transactions are 32-bit PCI transactions

performed by the pci_mt64 and pci_t64 MegaCore

functions.

For all memory write transactions, the following sequence of events is the

same:

1. The address phase occurs when the PCI master asserts framen (and

req64n in the case of a 64-bit transaction) and drives the address on

ad[31..0] and the command on cben[3..0]. Asserting req64n

indicates to the target device that the master device is requesting a

64-bit data transaction.

2. If the address of the transaction matches the memory range

specified in a base address register, the PCI MegaCore function

turns on the drivers for the ad bus, devseln, trdyn, stopn, and

par (as well as par64 and ack64n for 64-bit transactions) in the

following clock cycle.

3. The PCI MegaCore function drives and asserts devseln (and

ack64n for 64-bit transactions) to indicate to the master device that

it is accepting the transaction.

4. One or more data phases follow, depending on the type of write

transaction.

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Altera PCI Compiler Manuale Utente Pagina 137