Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Manuale Utente Scaricare il pdf (Pagina 62)

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Mentor VIP AE AXI3/4 User Guide, V10.2b

SystemVerilog AXI3 and AXI4 Master BFMs

create_write_transaction()

September 2013

create_write_transaction()

This nonblocking function creates a write transaction with a start address addr and optional

burst_length arguments. All other transaction fields default to legal protocol values, unless

previously assigned a value. It returns with the *_transaction record.

Prototype

// * = axi | axi4

// ** = AXI | AXI4

function automatic *_transaction create_write_transaction

(

input bit [((**_ADDRESS_WIDTH) - 1):0] addr,

bit [3:0] burst_length = 0 // optional

);

Arguments addr Start address

burst_length (Optional) Burst length. Default: 0.

Protocol

Transaction

Fields

size Burst size. Default: width of bus:

**_BYTES_1;

**_BYTES_2;

**_BYTES_4;

**_BYTES_8;

**_BYTES_16;

**_BYTES_32;

**_BYTES_64;

**_BYTES_128;

burst Burst type:

**_FIXED;

**_INCR; (default)

**_WRAP;

**_BURST_RSVD;

lock Burst lock:

**_NORMAL; (default)

**_EXCLUSIVE;

(AXI3) AXI_LOCKED;

(AXI3) AXI_LOCK_RSVD;

cache (AXI3) Burst cache:

AXI_NONCACHE_NONBUF; (default)

AXI_BUF_ONLY;

AXI_CACHE_NOALLOC;

AXI_CACHE_BUF_NOALLOC;

AXI_CACHE_RSVD0;

AXI_CACHE_RSVD1;

AXI_CACHE_WTHROUGH_ALLOC_R_ONLY;

AXI_CACHE_WBACK_ALLOC_R_ONLY;

AXI_CACHE_RSVD2;

AXI_CACHE_RSVD3;

AXI_CACHE_WTHROUGH_ALLOC_W_ONLY;

AXI_CACHE_WBACK_ALLOC_W_ONLY;

AXI_CACHE_RSVD4;

AXI_CACHE_RSVD5;

AXI_CACHE_WTHROUGH_ALLOC_RW;

AXI_CACHE_WBACK_ALLOC_RW;

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Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Manuale Utente Pagina 62

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