Altera Cyclone V GX FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 52)

2–44 Chapter 2: Board Components

Memory

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

FLASH_CLK

M9 2.5-V Clock

FLASH_OEN

M8 2.5-V Output enable

FLASH_RDYBSYN

L11 2.5-V Ready

FLASH_RESETN

L9 2.5-V Reset

FLASH_WEN

J15 2.5-V Write enable

FLASH_WPN

— 2.5-V Write protect

FSM_A1

N10 2.5-V Address bus

FSM_A2

N9 2.5-V Address bus

FSM_A3

M12 2.5-V Address bus

FSM_A4

M11 2.5-V Address bus

FSM_A5

G7 2.5-V Address bus

FSM_A6

G8 2.5-V Address bus

FSM_A7

F6 2.5-V Address bus

FSM_A8

G6 2.5-V Address bus

FSM_A9

J10 2.5-V Address bus

FSM_A10

K10 2.5-V Address bus

FSM_A11

E6 2.5-V Address bus

FSM_A12

E7 2.5-V Address bus

FSM_A13

D6 2.5-V Address bus

FSM_A14

D7 2.5-V Address bus

FSM_A15

A2 2.5-V Address bus

FSM_A16

A3 2.5-V Address bus

FSM_A17

D8 2.5-V Address bus

FSM_A18

E8 2.5-V Address bus

FSM_A19

F8 2.5-V Address bus

FSM_A20

G9 2.5-V Address bus

FSM_A21

H9 2.5-V Address bus

FSM_A22

J9 2.5-V Address bus

FSM_A23

H7 2.5-V Address bus

FSM_A24

J7 2.5-V Address bus

FSM_A25

A4 2.5-V Address bus

FSM_A26

A5 2.5-V Address bus

FSM_D0

E13 2.5-V Data bus

FSM_D1

F13 2.5-V Data bus

FSM_D2

C6 2.5-V Data bus

FSM_D3

C7 2.5-V Data bus

FSM_D4

A6 2.5-V Data bus

FSM_D5

B6 2.5-V Data bus

FSM_D6

A8 2.5-V Data bus

Table 2–32. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Board

Reference (U18)

Schematic Signal Name

Cyclone V GX

Pin Number

I/O Standard Description

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 58 59 60

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Altera Cyclone V GX FPGA Development Board Manuale Utente Pagina 52

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