Altera Cyclone V GX FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 42)

2–34 Chapter 2: Board Components

Memory

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

Table 2–29 lists the DDR3A pin assignments, signal names, and functions. The signal

names and types are relative to the Cyclone V GX in terms of I/O setting and

direction.

Table 2–29. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board Reference

Schematic

Signal Name

Cyclone V GX

Pin Number

I/O Standard Description

DDR3 x16 (U21)

DDR3A_A0

AJ12 1.5-V SSTL Class I Address bus

DDR3A_A1

AK12 1.5-V SSTL Class I Address bus

DDR3A_A2

AH11 1.5-V SSTL Class I Address bus

DDR3A_A3

AH12 1.5-V SSTL Class I Address bus

DDR3A_A4

AG13 1.5-V SSTL Class I Address bus

DDR3A_A5

AG14 1.5-V SSTL Class I Address bus

DDR3A_A6

AK10 1.5-V SSTL Class I Address bus

DDR3A_A7

AK11 1.5-V SSTL Class I Address bus

DDR3A_A8

AF11 1.5-V SSTL Class I Address bus

DDR3A_A9

AG11 1.5-V SSTL Class I Address bus

DDR3A_A10

AJ8 1.5-V SSTL Class I Address bus

DDR3A_A11

AK8 1.5-V SSTL Class I Address bus

DDR3A_A12

AJ7 1.5-V SSTL Class I Address bus

DDR3A_A13

AK7 1.5-V SSTL Class I Address bus

DDR3A_BA0

AH9 1.5-V SSTL Class I Bank address bus

DDR3A_BA1

AH10 1.5-V SSTL Class I Bank address bus

DDR3A_BA2

AJ10 1.5-V SSTL Class I Bank address bus

DDR3A_CASN

AF9 1.5-V SSTL Class I Row address select

DDR3A_CKE

AK18 1.5-V SSTL Class I Column address select

DDR3A_CLK_P

Y13

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3A_CLK_N

AA14

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3A_CSN

Y12 1.5-V SSTL Class I Chip select

DDR3A_DM0

AE15 1.5-V SSTL Class I Write mask byte lane

DDR3A_DM1

AH19 1.5-V SSTL Class I Write mask byte lane

DDR3A_DQ0

AF15 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ1

AE16 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ2

AJ14 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ3

AH15 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ4

AE17 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ5

AD17 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ6

AJ15 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ7

AF14 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ8

AK17 1.5-V SSTL Class I Data bus byte lane 1

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 59 60

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Altera Cyclone V GX FPGA Development Board Manuale Utente Pagina 42

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