Altera Cyclone V GX FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 24)

2–16 Chapter 2: Board Components

Setup Elements

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

Setup Elements

The development board includes several different kinds of setup elements. This

section describes the following setup elements:

■ Board settings DIP switch

■ JTAG settings DIP switch

■ PCI Express control DIP switch

■ CPU reset push button

■ MAX V reset push button

■ Program configuration push button

■ Program select push button

Board Settings DIP Switch

The board settings DIP switch (SW3) controls various features specific to the board

and the MAX V CPLD 5M2210 System Controller logic design. Table 2–8 lists the

switch controls and descriptions.

JTAG Chain Control DIP Switch

The JTAG chain control DIP switch (SW5) either remove or include devices in the

active JTAG chain. The Cyclone V GX FPGA is always in the JTAG chain. Table 2–9

lists the switch controls and its descriptions.

Table 2–8. Board Settings DIP Switch Controls

Switch Schematic Signal Name Description Default

CLK_SEL

ON : Select SMA input clock

OFF : Select programmable oscillator clock

OFF

CLK_EN

ON : Disable on-board oscillator

OFF : Enable on-board oscillator

OFF

FACT_LOAD

ON : Load the user design from flash at power up.

OFF : Load the factory design from flash at power up.

OFF

SEC_MODE

ON : Embedded USB-Blaster II sends FACTORY command at power up.

OFF : Embedded USB-Blaster II does not send FACTORY command at

power up.

OFF

Table 2–9. JTAG Chain Control DIP Switch

Switch Schematic Signal Name Description Default

5M2210_JTAG_EN

ON : Bypass MAX V CPLD 5M2210 System Controller

OFF : MAX V CPLD 5M2210 System Controller in-chain

OFF

HSMA_JTAG_EN

ON : Bypass HSMC port A

OFF : HSMC port A in-chain

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