Altera 50G Interlaken MegaCore Function Manuale Utente Pagina 2
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Contents
About This MegaCore Function......................................................................... 1-1
Features......................................................................................................................................................... 1-1
IP Core Supported Combinations of Number of Lanes and Data Rate...................................1-2
IP Core Raw Aggregate Bandwidth...............................................................................................1-2
Device Family Support................................................................................................................................1-2
IP Core Verification.....................................................................................................................................1-3
Performance and Resource Utilization.....................................................................................................1-3
Device Speed Grade Support......................................................................................................................1-4
Release Information.....................................................................................................................................1-4
Getting Started With the 50G Interlaken IP Core..............................................2-1
Installing and Licensing IP Cores..............................................................................................................2-1
OpenCore Plus IP Evaluation........................................................................................................ 2-1
Specifying the 50G Interlaken IP Core Parameters and Options .........................................................2-2
Files Generated for Arria V GZ and Stratix V Variations......................................................................2-3
Files Generated for Arria 10 Variations....................................................................................................2-4
Simulating the50G Interlaken IP Core......................................................................................................2-6
Integrating Your IP Core in Your Design................................................................................................ 2-6
Pin Assignments...............................................................................................................................2-6
Transceiver Logical Channel Numbering.....................................................................................2-7
Adding the Reconfiguration Controller..................................................................................... 2-10
Adding the External PLL.............................................................................................................. 2-12
Compiling the Full Design and Programming the FPGA....................................................................2-14
50G Interlaken IP Core Parameter Settings.......................................................3-1
Meta Frame Length in Words....................................................................................................................3-1
Transceiver Reference Clock Frequency...................................................................................................3-1
Number of Calendar Pages.........................................................................................................................3-2
TX Scrambler Seed.......................................................................................................................................3-2
Transfer Mode Selection.............................................................................................................................3-2
Functional Description....................................................................................... 4-1
Interfaces Overview.....................................................................................................................................4-1
Application Interface.......................................................................................................................4-1
Interlaken Interface..........................................................................................................................4-1
Out-of-Band Flow Control Interface.............................................................................................4-2
Management Interface.................................................................................................................... 4-2
Transceiver Control Interfaces.......................................................................................................4-2
High Level Block Diagram..........................................................................................................................4-4
Clocking and Reset Structure for IP Core................................................................................................ 4-4
TOC-2
About This MegaCore Function
Altera Corporation
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 8
- Release Information 8
- Altera IP Core Release Notes 9
- OpenCore Plus IP Evaluation 10
- UG-01140 11
- 2015.05.04 11
- Related Information 12
- 10 variation 13
- Pin Assignments 15
- Send Feedback 16
- Altera Corporation 16
- Adding the External PLL 21
- 50G Interlaken IP Core 22
- Meta Frame Length in Words 24
- Number of Calendar Pages 25
- TX Scrambler Seed 25
- Transfer Mode Selection 25
- Functional Description 27
- Management Interface 28
- High Level Block Diagram 30
- IP Core Reset 31
- Interleaved and Packet Modes 33
- 50G Interlaken IP Core TX MAC 40
- 50G Interlaken IP Core TX PCS 40
- 50G Interlaken IP Core TX PMA 40
- 50G Interlaken IP Core RX PMA 45
- 50G Interlaken IP Core RX PCS 45
- 50G Interlaken IP Core RX MAC 45
- Signal Name Direction Width 47
- Description 47
- Device Dependent Signals 60
- Offset Name R/W Description 63
- Example Design 68
- Top Testbench 68
- Testbench Simulation Behavior 70
- Internal Serial Loopback Mode 72
- External Loopback Mode 72
- CRC32 Error Injection 78
- Advanced Parameter Settings 79
- Counter Reset Bits 80
- Include Temp Sense 80
- RXFIFO Address Width 80
- Use ATX or CMU PLL 82
- Lane Profile 82
- MegaCore Function 84
- Ethernet Traffic 89
- Additional Information 91
- How to Contact Altera 93
- Typographic Conventions 93
- Visual Cue Meaning 94
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