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BAR Hit Signals
Signal Direction Description
rx_st_bar_hit_
tlp0[7:0]
rx_st_bar_hit_
tlp1[7:0]
Output Identifies the matching BAR for the TLP driven on the Avalon-
ST RX interface. Valid for MRd, MWr and Atomic Op TLPs. rx_
st_bar_hit_tlp<n>[7:0] should be ignored for all other TLPs.
Valid in the first cycle of a TLP, when rx_st_valid_app and any
bit of rx_st_sop_app are asserted. rx_st_bar_hit_tlp0 applies
to the TLP that starts on bits [127:0] . rx_st_bar_hit_tlp1
applies to the TLP that starts on bits [255:128].
The following encodings are defined:
• 0x01: BAR 0 when configured as 32-bit BAR. Or BAR 0-1
when configured as 64-bit BAR.
• 0x02: BAR 1 when configured as 32-bit BAR. Reserved when
BAR 1 is combined with BAR 0 to form a 64-bit BAR.
• 0x04: BAR 2 when configured as 32-bit BAR. Or BAR 2-3
when configured as 64-bit BAR.
• 0x08: BAR 3 when configured as 32-bit BAR. Reserved when
BAR 2 is combined with BAR 3 to form a 64-bit BAR.
• 0x10: BAR4 when configured as 32-bit BAR. Or BAR 4-5
when configured as 64-bit BAR.
• 0x20: BAR5 when configured as 32-bit BAR. Reserved when
BAR 4 is combined with BAR 5 to form a 64-bit BAR.
• 0x40 and 0x80: Reserved.
When rx_st_bar_hit_tlp0 orrx_st_bar_hit_tlp1 indicates
the address of a PF, the BAR number above should be interpreted
as a PF BAR. When rx_st_bar_hit_tlp0 orrx_st_bar_hit_
tlp1provides the address of a VF (indicating a VF hit), the BAR
number should be interpreted as a VF BAR.
These signals are required to support multiple packets per cycle.
The SR-IOV implementation does not support multiple packets
per cycle. Consequently, these signals are not used.
rx_st_bar_hit_fn_
tlp0[7:0]
rx_st_bar_hit_fn_
tlp1[7:0]
output Identifies the Function number that was hit by a TLP driven on
the Avalon-ST RX interface. These outputs are valid for MRd,
MWr and Atomic Op TLPs. Theses and are to be ignored for all
other TLPs.
rx_st_bar_hit_fn_tlp<n> is valid in the first cycle of a TLP,
when rx_st_valid_app and any bit of rx_st_sop_app are
asserted. rx_st_bar_hit_fn_tlp0[7:0] applies to the TLP that
starts on bits [127:0]. rx_st_bar_hit_fn_tlp1[7:0] applies to
the TLP that starts on bits [255:128].
4-8
BAR Hit Signals
UG-01097_sriov
2014.12.15
Altera Corporation
Interfaces and Signal Descriptions
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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