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Parameter Value Description
Prefetch‐
able
Prefetchable
Non-Prefetchable
Defining memory as prefetchable allows data in the
region to be fetched ahead anticipating that the
requestor may require more data from the same
region than was originally requested. If you specify
that a memory is prefetchable, it must have the
following 2 attributes:
• Reads do not have side effects
• Write merging is allowed
Size 16 Bytes–2 GBytes Specifies the memory size.
Device Identification Registers
Table 3-3: Device ID Registers
The following table lists the default values of the read-only Device ID registers. You can use the parameter editor
to change the values of these registers. At run time, you can change the values of these registers using the optional
reconfiguration block signals. You can specify Device ID registers for each Physical Function.
Register Name Range Default Value Description
Vendor ID 16 bits 0x00000000 Sets the read-only value of the Vendor ID register. This
parameter can not be set to 0xFFFF per the PCI Express
Specification.
Address offset: 0x000.
Device ID 16 bits 0x00000000 Sets the read-only value of the Device ID register.
Address offset: 0x000.
Revision ID 8 bits 0x00000000 Sets the read-only value of the Revision ID register.
Address offset: 0x008.
Class code 24 bits 0x00000000 Sets the read-only value of the Class Code register.
Address offset: 0x008.
Subsystem
Vendor ID
16 bits 0x00000000 Sets the read-only value of the Subsystem Vendor ID
register in the PCI Type 0 Configuration Space. This
parameter cannot be set to 0xFFFF per the PCI Express
Base Specification. This value is assigned by PCI-SIG to
the device manufacturer.
Address offset: 0x02C.
3-6
Device Identification Registers
UG-01097_sriov
2014.12.15
Altera Corporation
Parameter Settings
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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