Altera Stratix IV GX FPGA Manuale Utente Scaricare il pdf (Pagina 27)

Chapter 6: Board Test System 6–3

Preparing the Board

March 2014 Altera Corporation Stratix IV GX FPGA Development Kit User Guide

1 The Board Test System and Power Monitor share the JTAG bus with other

applications like the Nios II debugger and the SignalTap

II Embedded Logic

Analyzer. Because the Quartus II programmer uses most of the bandwidth of the

JTAG bus, other applications using the JTAG bus might time out. Be sure to close the

other applications before attempting to reconfigure the FPGA using the Quartus II

Programmer.

Preparing the Board

With the power to the board off, perform the following steps:

1. Connect the USB cable to the board.

2. Verify the settings for the board settings DIP switch bank (SW4) match Table 4–2

on page 4–3.

3. Set the rotary switch (SW2) to the 1 position.

4. Verify the settings for the JTAG DIP switch bank (SW6), located on the back of the

board, match Table 4–4 on page 4–5. These settings determine the devices to

include in the JTAG chain.

f For more information about the board’s DIP switch and jumper settings,

refer to the Stratix IV GX FPGA Development Board Reference Manual.

5. Turn on the power to the board. The board loads the design stored in the user

hardware portion of flash memory into the FPGA.

c To ensure operating stability, keep the USB cable connected and the board

powered on when running the demonstration application. The application

cannot run correctly unless the USB cable is attached and the board is on.

Running the Board Test System

To run the application, navigate to the <install

dir>\kits\stratixIVGX_4sgx230_fpga\examples\board_test_system directory and

run the BoardTestSystem.exe application.

1 On Windows, click Start > All Programs > Altera > Stratix IV GX FPGA

Development Kit <version> > Board Test System to run the application.

A GUI appears, displaying the application tab that corresponds to the design running

in the FPGA. The Stratix IV GX FPGA development board’s flash memory ships

preconfigured with the design that corresponds to the Config, GPIO, and

SRAM&Flash tabs.

1 If you power up your board with the rotary switch (SW2) in a position other than the

1 position, or if you load your own design into the FPGA with the Quartus II

Programmer, you receive a message prompting you to configure your board with a

valid Board Test System design. Refer to “The Configure Menu” for information about

configuring your board.

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Altera Stratix IV GX FPGA Manuale Utente Pagina 27