Altera RapidIO MegaCore Function Manuale Utente Scaricare il pdf (Pagina 34)

2–12 Chapter 2: Getting Started

Instantiating Multiple RapidIO IP Cores

RapidIO MegaCore Function August 2014 Altera Corporation

User Guide

Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX,

and Stratix IV GX Variations

RapidIO IP cores that target an Arria II GX, Arria II GZ, Cyclone IV GX, or Stratix IV

GX device all instantiate an ALTGX transceiver megafunction to configure the device

transceivers. When your design contains multiple IP cores that use the ALTGX

megafunction, you must ensure that the

cal_blk_clk

and

gxb_powerdown

input

signals are connected properly.

You must ensure that the

cal_blk_clk

input to each RapidIO IP core (or any other

megafunction or user logic that uses the ALTGX megafunction) is driven by the same

calibration clock source.

When you merge multiple RapidIO IP cores in a single transceiver block, the same

signal must drive

gxb_powerdown

to each of the RapidIO IP core variations and other

megafunctions, IP cores, and user logic that use the ALTGX megafunction.

To successfully combine multiple high-speed transceiver channels in the same

transceiver block, they must have the same dynamic reconfiguration setting. If two IP

cores implement dynamic reconfiguration in the same transceiver block of an

Arria II GX, Arria II GZ, Cyclone IV GX, or Stratix IV GX device, the parameters or

characteristics that you want to control with the dynamic reconfiguration

megafunction instance must be identical.

To support the dynamic reconfiguration block, turn on Analog controls on the

Reconfiguration Settings tab in the transceiver parameter editor. Arria II GX,

Arria II GZ, Cyclone IV GX, and Stratix IV GX device transceivers require a dynamic

reconfiguration block, to support offset cancellation.

Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP

Core Instances

When you instantiate multiple RapidIO IP core instances in your design, you must

modify the Synopsys Design Constraints File (.sdc) to repeat the

create_generated_clock

statements for each IP core instance. The statements must

include the full name of the variation in the clock names.

If you do not do this, the source and destination clocks each have multiple matches;

the

rxclk

and

clk_div_by_2

filters match the relevant clocks in all of the IP core

instances.

Sourcing Multiple Tcl Scripts for non-Arria 10 Variations

If you use Altera-provided Tcl scripts to specify constraints for IP cores, you must run

the Tcl script associated with each generated RapidIO IP core. For example, if a system

has

rio1

and

rio2

IP core variations, then you must source rio1_constraints.tcl,

execute the

add_rio_constraints

command and then source rio2_constraints.tcl and

run the

add_rio_constraints

command, sequentially, from the Tcl console after

generation.

1 2 ... 29 30 31 32 33 34 35 36 37 38 39 ... 197 198

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Altera RapidIO MegaCore Function Manuale Utente Pagina 34

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