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Info–2 Additional Information
Document Revision History
RapidIO MegaCore Function August 2014 Altera Corporation
User Guide
June 2014
(continued)
Continued on
next page
14.0
■ Removed support for Physical-layer only variations. The RapidIO IP core no longer
supports Physical-layer only variations.
■ Removed information about the Atlantic interface, which is no longer visible at the top
level. Removed information from “OpenCore Plus Time-Out Behavior” on page 1–13,
Chapter 4, Functional Description, Chapter 5, Signals, and Chapter 7, Testbenches. For
example, modified the description of the Atlantic interface to retain only a description of
the Physlcal layer buffers.
■ Removed information about clocking, reset, and testbench for Physical-layer only
variations. Removed information from Chapter 4, Functional Description and Chapter 7,
Testbenches. In Chapter 4, Functional Description, modified Figure 4–5 on page 4–11,
combined separate clocking sections for the Physlcal-layer only variations and other
variations and combined separate reset sections. In Chapter 7, Testbenches, removed
information about the Physical-layer only testbench.
■ Removed the PHY Maintenance Avalon-MM slave interface signals (
phy_mnt_s_clk,
phy_mnt_s_chipselect, phy_mnt_s_waitrequest, phy_mnt_s_read,
phy_mnt_s_write, phy_mnt_s_addresss, phy_mnt_s_writedata,
phy_mnt_s_readdata
). This interface is no longer a top-level interface. In variations
with a Transport layer, software accesses the Physical layer registers through the
system maintenance Avalon-MM slave interface instead.
■ Removed the “Calculating Resource Utilization for Modular Configurations” appendix.
■ Corrected the description of the
atxwlevel
,
atxovf
, and
arxwlevel
Physical-layer
buffer status output signals to indicate they are available. These signals were previously
described incorrectly as being available only in Physical-layer-only variations.
■ Added section “Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP
Core Instances” on page 2–12. This section describes an additional requirement for
ensuring a design with multiple RapidIO IP core instances functions correctly.
■ Added new section “Avalon-MM Interface Widths in the RapidIO IP Core” on page 4–1.
■ Clarified that
sys_mnt_s_address
,
mnt_s_address
, and
drbell_s_address
are word
addresses and not byte addresses. They each address a four-byte (32-bit) word. Modified
Maintenance TX address window translation calculation accordingly in “Maintenance
Module”.
■ Corrected the width of
mnt_s_address
to 24 bits in Table 5–13 on page 5–11 and in the
Maintenance TX address window translation calculation description in “Maintenance
Module”.
■ Clarified that
io_s_wr_address
and
io_s_rd_address
are word addresses (and not
byte addresses) in RapidIO 1x variations, and are double-word addresses in 2x and 4x
variations, in Table 5–16 on page 5–12 and Table 5–17 on page 5–13, respectively.
Corrected header and note in Table 4–11 on page 4–48 and Table 4–12 on page 4–49 to
specify that the bit that provides the wdptr information is bit [0] rather than bit [2].
Corrected address window translation calculation and examples accordingly in
“Input/Output Avalon-MM Slave Module” on page 4–41.
■ Updated parameter descriptions in Chapter 3, Parameter Settings.
■ Updated capitalization and minor changes in parameter names.
■ Transceiver selection is no longer modifiable. The remaining supported device families
do not support an external transceiver option.
■ Removed the Transceiver Configuration option.
■ Removed Enable Transport Layer parameter. The RapidIO IP core no longer supports
Physical-layer only variations: all variations have a Transport layer.
■ Removed EDA Settings and Summary sections. These tabs no longer exist in the
RapidIO parameter editor in the new Quartus II software v14.0 IP design flow.
Date Version Changes
- User Guide 1
- RapidIO MegaCore Function 1
- Contents 3
- Contents v 5
- Chapter 5. Signals 6
- Chapter 6. Software Interface 6
- Chapter 7. Testbenches 6
- Releases 10
- RapidIO IP Core Features 10
- Features 11
- Device Family Support 12
- Note to Table 1–2: 13
- Interoperability Testing 14
- Note to Table 1–4: 16
- Notes to Table 1–7: 18
- Notes to Table 1–8: 19
- Installation and Licensing 20
- 2. Getting Started 23
- Simulating IP Cores 26
- Calibration Clock 27
- Transceiver Settings 28
- IV GX Variations 28
- External Transceiver PLL 29
- Specifying Constraints 30
- Variations 32
- Core Instances 34
- Mode Selection 37
- Transceiver Selection 38
- Baud Rate 39
- Reference Clock Frequency 39
- Receive Buffer Size 39
- Transmit Buffer Size 39
- Enable 16-Bit Device ID Width 40
- Destination ID Checking 40
- Maintenance Logical Layer 41
- Port Write Tx Enable 42
- Port Write Rx Enable 42
- Avalon-MM Master 43
- Avalon-MM Slave 43
- Doorbell Slave 43
- Device ID 44
- Vendor ID 44
- Revision ID 44
- Processing Element Features 45
- Switch Support 45
- Enable Switch Support 46
- Number of Ports 46
- Port Number 46
- Source Operation 46
- Destination Operation 46
- 4. Functional Description 47
- Interfaces 48
- Avalon System Clock 49
- Reference Clock 50
- Other Input Clocks 51
- Clock Domains 51
- Notes to Figure 4–2: 52
- Notes to Table 4–2: 52
- Reset for RapidIO IP Cores 53
- Reset Controller 54
- Clocking and Reset Structure 55
- Physical Layer 56
- Physical Layer Architecture 57
- Receiver Transceiver 58
- CRC Checking and Removal 58
- Transmitter Transceiver 59
- Physical Layer Receive Buffer 60
- Transport Layer 65
- Receiver 66
- Transaction ID Ranges 67
- Concentrator Register Module 69
- Maintenance Module 72
- Maintenance Register 74
- Maintenance Slave Processor 74
- Maintenance Master Processor 76
- Port-Write Processor 78
- Registers Location 81
- Transactions 82
- Notes to Table 4–8: 84
- Notes to Table 4–9: 85
- Note to Figure 4–22: 91
- Notes to Table 4–11: 95
- Notes to Table 4–12: 96
- Note to Table 4–13: 96
- Notes to Table 4–14: 97
- Doorbell Module Block Diagram 99
- Preserving Transaction Order 100
- Doorbell Message Generation 101
- Doorbell Message Reception 102
- Note to Figure 4–30: 103
- 29’hb4b5959 104
- CRC field is not removed 105
- Note to Table 4–15: 105
- Logical Layer Modules 106
- Protocol Violations 108
- Fatal Errors 108
- Maintenance Avalon-MM Slave 109
- Maintenance Avalon-MM Master 110
- Port-Write Reception Module 111
- Input/Output Avalon-MM Slave 111
- Input/Output Avalon-MM Master 112
- Note to Table 5–2: 115
- 5–2 Chapter 5: Signals 116
- Physical Layer Signals 116
- Multicast Event Signals 117
- Note to Table 5–6: 118
- Notes to Table 5–7: 118
- Chapter 5: Signals 5–5 119
- 5–6 Chapter 5: Signals 120
- Notes to Table 5–8: 121
- 5–8 Chapter 5: Signals 122
- Chapter 5: Signals 5–9 123
- Register-Related Signals 124
- Avalon-MM Interface Signals 124
- Chapter 5: Signals 5–11 125
- 4x variations 126
- 2x and 4x variations 126
- Chapter 5: Signals 5–13 127
- Note to Table 5–19: 128
- Notes to Table 5–20: 129
- 5–16 Chapter 5: Signals 130
- Notes to Table 5–21: 131
- 5–18 Chapter 5: Signals 132
- 6. Software Interface 133
- Physical Layer Registers 136
- Note to Table 6–10: 141
- Note to Table 6–11: 143
- Note to Table 6–12: 143
- Note to Table 6–13: 144
- Note to Table 6–14: 144
- Note to Table 6–15: 144
- Note to Table 6–16: 145
- Note to Table 6–17: 145
- Notes to Table 6–18: 146
- Notes to Table 6–19: 147
- Note to Table 6–22: 148
- Note to Table 6–23: 148
- Note to Table 6–24: 148
- Receive Maintenance Registers 149
- Transmit Port-Write Registers 150
- Receive Port-Write Registers 151
- Note to Table 6–45: 154
- Note to Table 6–51: 156
- Doorbell Message Registers 158
- Note to Table 6–63: 160
- 7. Testbenches 163
- 7–2 Chapter 7: Testbenches 164
- Chapter 7: Testbenches 7–3 165
- 7–4 Chapter 7: Testbenches 166
- SWRITE Transactions 167
- NWRITE_R Transactions 168
- NWRITE Transactions 169
- NREAD Transactions 170
- Doorbell Transactions 170
- Chapter 7: Testbenches 7–9 171
- Port-Write Transactions 172
- Chapter 7: Testbenches 7–11 173
- 7–12 Chapter 7: Testbenches 174
- 8. Qsys Design Example 175
- Running Qsys 177
- Adding the Master I/O BFM 181
- Adding the On-Chip Memory 182
- Connecting Unconnected Clocks 183
- Connecting System Components 183
- Generating the System 185
- Simulating the System 186
- A. Initialization Sequence 187
- Additional Information 193
- Info–2 Additional Information 194
- Document Revision History 194
- Additional Information Info–3 195
- Info–4 Additional Information 196
- Note to Table: 197
- Typographic Conventions 198
- Info–6 Additional Information 198
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