Altera QDRII SRAM Controller MegaCore Function Manuale Utente Scaricare il pdf (Pagina 43)

Altera Corporation MegaCore Version 9.1 3–11

November 2009 QDRII SRAM Controller MegaCore Function User Guide

Functional Description

■ Writes

■ Reads

■ Simultaneous Read & Write Timing

f For more information on the Avalon interface, refer to the Avalon

Interface Specifications.

Writes

This section discusses the following topics:

■ “Isolated Write” on page 3–11

■ “Bursts” on page 3–13

■ “Bursts with Pauses” on page 3–14

If the address is the consecutive, you can have consecutive write cycles

(refer to “Bursts” on page 3–13). Non-consecutive addresses are split

into two transfers and you must pause a transfer (refer to “Bursts with

Pauses” on page 3–14).

Isolated Write

Figure 3–7 shows an isolated write transaction on a burst of four (narrow

mode). The Avalon interface receives a write request, which the

controller immediately accepts. It then transfers the write data (the exact

timing may vary) to the QDRII SRAM interface. As it receives only half

the required data for a burst of four, it masks the second part of the burst

on the QDRII SRAM interface as invalid.

Figure 3–7. Isolated Write—Burst of Four (Narrow Mode)

clk

avl_write

avl_data_wr[35:0]

avl_adr_wr[19:0]

avl_wait_request_wr

write_clk

system_clk

qdrii_d[17:0]

qdrii_a[19:0]

qdrii_bwsn[1:0]

qdrii_wpsn

0001000200010002

00010001

0001 00020002

00010001

00 1111

1 2 ... 38 39 40 41 42 43 44 45 46 47 48 ... 67 68

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Altera QDRII SRAM Controller MegaCore Function Manuale Utente Pagina 43