Altera QDRII SRAM Controller MegaCore Function Manuale Utente Scaricare il pdf (Pagina 3)

Altera Corporation MegaCore Version 9.1 iii

Contents

Chapter 1. About This MegaCore Function

Release Information ............................................................................................................................... 1–1

Device Family Support ......................................................................................................................... 1–1

Features ................................................................................................................................................... 1–2

General Description ............................................................................................................................... 1–2

OpenCore Plus Evaluation .............................................................................................................. 1–3

Performance and Resource Utilization ............................................................................................... 1–4

Chapter 2. Getting Started

Design Flow ............................................................................................................................................ 2–1

QDRII SRAM Controller Walkthrough .............................................................................................. 2–2

Create a New Quartus II Project .................................................................................................... 2–3

Launch IP Toolbench ....................................................................................................................... 2–4

Step 1: Parameterize ......................................................................................................................... 2–5

Step 2: Constraints ............................................................................................................................ 2–7

Step 3: Set Up Simulation ................................................................................................................ 2–7

Step 4: Generate ................................................................................................................................ 2–8

Simulate the Example Design ............................................................................................................ 2–11

Simulate with IP Functional Simulation Models ....................................................................... 2–11

Simulating With the ModelSim Simulator ................................................................................. 2–11

Simulating With Other Simulators .............................................................................................. 2–12

Simulating in Third-Party Simulation Tools Using NativeLink ............................................. 2–17

Edit the PLL .......................................................................................................................................... 2–18

Compile the Example Design ............................................................................................................ 2–19

Program a Device ................................................................................................................................ 2–21

Implement Your Design ..................................................................................................................... 2–21

Set Up Licensing .................................................................................................................................. 2–21

Chapter 3. Functional Description

Block Description ................................................................................................................................... 3–1

Control Logic .................................................................................................................................... 3–2

Resynchronization & Pipeline Logic ............................................................................................. 3–3

Datapath ............................................................................................................................................ 3–5

OpenCore Plus Time-Out Behavior .................................................................................................. 3–10

Interfaces & Signals ............................................................................................................................. 3–10

Interface Description ...................................................................................................................... 3–10

Signals .............................................................................................................................................. 3–22

Device-Level Configuration ............................................................................................................... 3–26

PLL Configuration ......................................................................................................................... 3–26

Example Design .............................................................................................................................. 3–27

Constraints ...................................................................................................................................... 3–29

1 2 3 4 5 6 7 8 ... 67 68

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