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Table 4-18: ECC Registers
Word Offset Register Name Description Access HW Reset
Value
0x0240 ecc_status
• Bit 0—a value of '1' indicates that an ECC
error was detected and corrected. Once
set, the client must write a '1' to this bit to
clear it.
• Bit 1—a value of '1' indicates that an ECC
error was detected but not corrected.
Once set, the client must write a '1' to this
bit to clear it.
• Bits 31:2—reserved.
RW1C 0x0
0x0241 ecc_enable
• Bit 0—specifies how detected and
corrected ECC errors are reported.
0: Reported by the ecc_status[0]
register bit only.
1: Reported by the ecc_status[0]
register bit and the ecc_err_det_corr
signal.
• Bit 1—specifies how detected and
uncorrected ECC errors are reported.
0: Reported by the ecc_status[0]
register bit only.
1: Reported by the ecc_status[0]
register bit and the ecc_err_det_uncorr
signal.
• Bits 31:2—reserved.
RW 0x0
Statistics Registers
Statistics counters with prefix tx_ collect statistics on the TX datapath; prefix rx_ collect statistics on the
RX datapath. The counters collect statistics for the following frames:
• Good frame—error-free frames with a valid frame length.
• Error frame—frames that contain errors or with an invalid frame length.
• Invalid frame—frames that are not supported by the MAC IP core. It may or may not contain error
within the frame or have an invalid frame length. The MAC drops invalid frames.
The statistics counters are 36 bits wide and counters occupy two offsets. The user application must first
read the lower 32 bits followed by the upper 4 bits.
• The lower 32 bits of the counter occupy the first offset.
• The upper 4 bits of the counter occupy bits 3:0 at the second offset.
• Bits 31:5 at the second offset are reserved.
UG-01144
2014.12.15
Statistics Registers
4-25
Configuration Registers for LL Ethernet 10G MAC
Altera Corporation
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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