Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manuale Utente Pagina 2
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Contents
About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY
MegaCore Function.........................................................................................1-1
Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features................... 1-2
Low Latency 40-100GbE IP Core Device Family and Speed Grade Support......................................1-4
Device Family Support....................................................................................................................1-4
Low Latency 40-100GbE IP Core Device Speed Grade Support...............................................1-5
IP Core Verification.....................................................................................................................................1-5
Simulation Environment................................................................................................................ 1-6
Compilation Checking....................................................................................................................1-6
Hardware Testing.............................................................................................................................1-6
Performance and Resource Utilization.....................................................................................................1-6
Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores.....................................1-7
Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores......................................1-8
Release Information...................................................................................................................................1-10
Getting Started.................................................................................................... 2-1
Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices......................................2-2
Installing and Licensing IP Cores..............................................................................................................2-3
OpenCore Plus IP Evaluation........................................................................................................ 2-3
Specifying the Low Latency 40-100GbE IP Core Parameters and Options.........................................2-3
IP Core Parameters......................................................................................................................................2-5
Files Generated for Stratix V Variations.................................................................................................2-13
Files Generated for Arria 10 Variations..................................................................................................2-14
Integrating Your IP Core in Your Design..............................................................................................2-17
Pin Assignments.............................................................................................................................2-18
External Transceiver Reconfiguration Controller Required in Stratix V Designs............... 2-18
External Transceiver PLL Required in Arria 10 Designs......................................................... 2-19
External Time-of-Day Module for Variations with 1588 PTP Feature..................................2-20
Clock Requirements for 40GBASE-KR4 Variations.................................................................2-21
External TX MAC PLL..................................................................................................................2-21
Placement Settings for the Low Latency 40-100GbE IP Core................................................. 2-21
Low Latency 40-100GbE IP Core Testbenches......................................................................................2-21
Low Latency 40-100GbE IP Core Testbench Overview........................................................... 2-22
Understanding the Testbench Behavior.....................................................................................2-26
Simulating the Low Latency 40-100GbE IP Core With the Testbenches.......................................... 2-27
Generating the Low Latency 40-100GbE Testbench................................................................ 2-28
Optimizing the Low Latency 40-100GbE IP Core Simulation With the Testbenches.........2-29
Simulating with the Modelsim Simulator...................................................................................2-29
Simulating with the NCSim Simulator....................................................................................... 2-30
Simulating with the VCS Simulator............................................................................................ 2-30
Testbench Output Example: Low Latency 40-100GbE IP Core..............................................2-30
TOC-2
About The Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function
Altera Corporation
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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