Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Manuale Utente Pagina 132
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Addr Name Bit Description HW Reset
Value
Access
0x606 TX_PAUSE_
REQUEST
[N-
1:0]
(9)
Pause request. If bit [n] of the TX_PAUSE_EN
register has the value of 1, setting bit [n] of
the TX_PAUSE_REQUEST register field to the
value of 1 triggers a XOFF pause packet
insertion into the TX data stream on the
Ethernet link. If the IP core implements
priority-based flow control, the XOFF pause
packet includes identity information for the
corresponding priority queue.
If RETRANSMIT_XOFF_HOLDOFF_EN is turned
on for the associated priority queue, as long
as the value in TX_PAUSE_REQUEST bit [n]
remains high, the IP core retransmits the
XOFF pause packet at intervals determined
by the retransmit hold-off value associated
with this priority queue.
If bit [n] of the TX_PAUSE_EN register has the
value of 1, resetting bit [n] of the TX_PAUSE_
REQUEST register field to the value of 0
triggers an XON pause packet insertion into
the TX data stream on the Ethernet link. If
the IP core implements priority-based flow
control, the XON pause packet includes
identity information for the corresponding
priority queue.
Other pause registers, described in this table,
specify the properties of the pause packets.
Altera recommends that you signal a pause
request using the pause_insert_tx signal
rather than using the TX_PAUSE_REQUEST
register.
0
RW
0x607 RETRANSMIT_
XOFF_
HOLDOFF_EN
[N-
1:0]
(9)
Enable XOFF pause frame retransmission
hold-off functionality. If your IP core
implements priority-based flow control with
multiple priority queues, this register
provides access to one bit for each priority
queue.
Altera recommends that you maintain this
register at the value of all ones.
If your IP core implements priority-based
flow control, refer also to the description of
the CFG_RETRANSMIT_HOLDOFF_EN and CFG_
RETRANSMIT_HOLDOFF_QUANTA registers.
N'b1...1 (1'b1
in each
defined bit)
RW
UG-01172
2015.05.04
Pause Registers
3-87
Functional Description
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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