Altera Cyclone V E FPGA Manuale Utente Scaricare il pdf (Pagina 13)

Chapter 4: Development Board Setup 4–3

Factory Default Switch Settings

December 2014 Altera Corporation Cyclone V E FPGA Development Kit

User Guide

2. Set the DIP switch bank (SW2) to match Table 4–2 and Figure 4–1.

3. Set the DIP switch bank (SW4) to match Table 4–3 and Figure 4–1.

f For more information about the FPGA board settings, refer to the Cyclone V E FPGA

Development Board Reference Manual.

Table 4–2. SW2 JTAG DIP Switch Settings

Switch

Board

Label

Function

Default

Position

1 FAN_FORCE_ON

■ ON (0) = Fan is turned on. (Fan not included.)

■ OFF (1) = Fan is turned off.

OFF

2 RESERVED — —

3 HSMA_JTAG_EN

■ ON (0) = Do not Include the HSMC port in the

JTAG chain.

■ OFF (1) = Include the HSMC port in the JTAG

chain.

4 5M2210_JTAG_EN

■ ON (0) = Do not Include MAX V system

controller in the JTAG chain.

■ OFF (1) = Include MAX V system controller in

the JTAG chain

OFF

Table 4–3. SW4 DIP Switch Settings

Switch

Board

Label

Function

Default

Position

1 CLK_SEL

■ ON (0) = Select programmable oscillator clock.

■ OFF (1) = Select SMA input clock.

2 CLK_EN

■ ON (0) = On-board oscillator is disabled.

■ OFF (1) = On-board oscillator is enabled.

OFF

3 FACT_LOAD

■ ON (0) = Load the user design from flash at

power up.

■ OFF (1) = Load the factory design from flash at

power up.

OFF

4 SECURITY

■ ON (0) = Embedded On-Board USB Blaster II

sends FACTORY command at power up.

■ OFF (1) = Embedded On-Board USB Blaster II

does not send FACTORY command at power

up.

OFF

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