Altera PHY IP Core Guida Utente Pagina 183
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- Indice
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Valutato. / 5. Basato su recensioni clienti
Chapter 10: Transceiver Reconfiguration Controller 10–17
ATX PLL Calibration
March 2012 Altera Corporation Altera Transceiver PHY IP Core
User Guide
Table 10–16 describes the AEQ registers that you can access to change AEQ settings.
1 All undefined register bits are reserved and must be set to 0.
Refer to “Changing Transceiver Settings Using Register-Based Reconfiguration” on
page 10–27 for the procedures you can use to control AEQ.
ATX PLL Calibration
This feature allows you to rerun ATX calibration after power up. The Transceiver
Reconfiguration Controller automatically runs ATX calibration at power up.
1 You may need to rerun ATX calibration if you reset an ATX PLL and it does not lock
after the specified lock time.
7’h2A
[9] R
control and status
Error
. When asserted, indicates an error. This bit is asserted
when the channel address is invalid.
[8] R
Busy
. When asserted, indicates that a reconfiguration
operation is in progress.
[1] W
Read
. Writing a 1 to this bit triggers a read operation.
[0] W
Write
. Writing a 1 to this bit triggers a write operation.
7’h2B [3:0] RW
aeq_offset
Specifies the address of the AEQ register to be read or
written. Refer to Table 10–16 for details.
7’h2C [15:0] RW
data
Specifies the read or write data.
Table 10–15. AEQ Registers (Part 2 of 2)
Recon
-fig
Addr
Bits R/W Register Name Description
Table 10–16. AEQ Offsets and Values
Offset Bits R/W Register Name Description
Default
Value
0x0
[8] R
adapt_done
When asserted, indicates that adaptation has
completed.
1b’0
[1:0] RW
mode
Specifies the following address modes:
■ 2’b00: Low power manual equalization mode
■ 2’b01: One-time AEQ adaptation at power up
■ 2’b10: Perform continuous AEQ adaptation
■ 2’b11: Reserved
2’b00
0x2 [3:0] R
equalization
results
This is the value set by the automatic AEQ
adaptation performed at startup. If you choose to
perform manual equalization using the linear
equalizer, you can use this value as a reference.
Although automatic and manual equalization do not
provide identical functionality, specifying this value
enables manual equalization to approximate the
original setting.
0x0000
- User Guide 1
- Contents 3
- Chapter 7. Custom PHY IP Core 5
- Contents vi 6
- 1. Introduction 9
- Stratix V Device 10
- Reset Controller 11
- Avalon-MM PHY Management 11
- 1–4 Chapter 1: Introduction 12
- Unsupported Features 13
- 1–6 Chapter 1: Introduction 14
- 2. Getting Started 15
- Note to Figure2–2: 16
- Simulate the IP Core 18
- 3. 10GBASE-R PHY IP Core 19
- Release Information 20
- Note to Table 3–1: 21
- Stratix IV Devices 23
- Stratix V Devices 24
- SDR XGMII TX Interface 30
- Note to Table 3–9: 30
- SDR XGMII RX Interface 31
- Note to Table 3–11: 31
- Status Interface 32
- Clocks, Reset, and Powerdown 32
- Serial Interface 35
- Note to Table 3–15: 35
- TimeQuest Timing Constraints 40
- Note to Figure4–1: 43
- Note to Table 4–1: 44
- Advanced Options 51
- Configurations 52
- PMA Channel Controller 58
- Stratix IV GX Devices 65
- 5. Interlaken PHY IP Core 67
- Analog Settings 70
- Note to Figure5–2: 74
- Avalon-ST TX Interface 75
- Avalon-ST RX Interface 76
- PLL Interface 78
- TX and RX Serial Interface 78
- Optional Clocks for Deskew 78
- Transceiver Reconfiguration 81
- General Options 84
- Note to Figure6–2: 90
- PIPE Interface 92
- Note to Table 6–8: 93
- Transceiver Serial Interface 94
- Registers 95
- 7. Custom PHY IP Core 101
- Device Family Support 102
- Parameter Settings 103
- Word Alignment 106
- Rate Match FIFO 107
- 8B/10B Encoder and Decoder 108
- Byte Ordering 108
- PLL Reconfiguration 109
- Analog Options 110
- Presets for Ethernet 114
- Interfaces 115
- Note to Figure7–2: 116
- Clock Interface 118
- Status Signals (Optional) 118
- Note to Table 7–17: 119
- Register Interface 120
- Register Descriptions 121
- Dynamic Reconfiguration 124
- 8. Low Latency PHY IP Core 125
- Note to Table 8–4: 129
- Note to Table 8–5: 130
- Serial Data Interface 137
- Optional Status Interface 138
- PMA and Light-Weight PCS 139
- Arria V or Stratix V FPGA 143
- Auto-Negotiation 144
- Delay Estimation Logic 145
- Note to Figure9–2: 145
- Delay Numbers 146
- Note to Table 9–4: 147
- Additional Options 150
- TX and RX Status Signals 159
- Deterministic PHY IP Core 161
- Controller 167
- Note to Figure10–1: 169
- Note to Table 10–6: 174
- Embedded 175
- Offset Cancellation 176
- Duty Cycle Calibration 176
- PMA Analog Controls 177
- Pre-CDR Reverse Serial 178
- Loopback 178
- Post-CDR Reverse Serial 178
- ATX PLL Calibration 183
- Channel Reconfiguration 187
- Streamer Module 188
- Stratix V MIF 191
- Register-Based Write 193
- Register-Based Read 193
- Direct Write Reconfiguration 195
- Figure 10–6. Sample MIF 196
- Example 10–5. (continued) 197
- Notes to Figure 10–14: 205
- Transceiver 206
- XAUI PHY 209
- Port Differences 210
- Note to Table 11–3: 212
- Note to Table 11–5: 215
- Custom PHY 216
- Note to Table 11–6: 217
- Note to Table 11–7: 218
- Additional Information 219
- Revision History 220
- Note to Table: 228
- Typographic Conventions 229
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