Altera Stratix IV GX FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 61)

Chapter 2: Board Components 2–53

Memory

November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual

Table 2–49 lists the DDR3 component reference and manufacturing information.

QDRII+ Top Port 0

The QDRII+ top port 0 consists of a single QDRII+ burst-of-4 SRAM, providing

4 Mbyte with an 18-bit read data bus and an 18-bit write data bus.

This memory interface is designed to run between 120 MHz, the minimum frequency

for this device, and 400 MHz for a maximum theoretical bandwidth of over 14.4 Gbps

for reading and 14.4 Gbps for writing. The internal bus in the FPGA is typically 2 or 4

times the width at full rate or half rate respectively. For example, a 400 MHz 18-bit

interface becomes a 200 MHz 72 bit bus.

U14.E3 Data bus byte lane 0

DDR3TOP_DQ0

1.5-V SSTL Class I

A10

U14.F7 Data bus byte lane 0

DDR3TOP_DQ1

D11

U14.F2 Data bus byte lane 0

DDR3TOP_DQ2

B10

U14.F8 Data bus byte lane 0

DDR3TOP_DQ3

C12

U14.H3 Data bus byte lane 0

DDR3TOP_DQ4

C11

U14.H8 Data bus byte lane 0

DDR3TOP_DQ5

C13

U14.G2 Data bus byte lane 0

DDR3TOP_DQ6

A11

U14.H7 Data bus byte lane 0

DDR3TOP_DQ7

B13

U14.E7 Write mask byte lane 0

DDR3TOP_DM0

B11

U14.F3 Data strobe P byte lane 0

DDR3TOP_DQS_P0

D14

U14.G3 Data strobe N byte lane 0

DDR3TOP_DQS_N0

C14

U14.D7 Data bus byte lane 1

DDR3TOP_DQ8

K22

U14.C3 Data bus byte lane 1

DDR3TOP_DQ9

D22

U14.C8 Data bus byte lane 1

DDR3TOP_DQ10

J22

U14.C2 Data bus byte lane 1

DDR3TOP_DQ11

E22

U14.A7 Data bus byte lane 1

DDR3TOP_DQ12

G22

U14.A2 Data bus byte lane 1

DDR3TOP_DQ13

F23

U14.B8 Data bus byte lane 1

DDR3TOP_DQ14

H22

U14.A3 Data bus byte lane 1

DDR3TOP_DQ15

D23

U14.D3 Write mask byte lane 1

DDR3TOP_DM1

G23

U14.C7 Data strobe P byte lane 1

DDR3TOP_DQS_P1

J23

U14.B7 Data strobe N byte lane 1

DDR3TOP_DQS_N1

H23

Table 2–48. DDR3 Top Port Pin Assignments, Signal Names and Functions (Part 2 of 2)

Board Reference Description Schematic Signal

Name

I/O Standard

Stratix IV GX

Device

Pin Number

Table 2–49. DDR3 Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U14 8 M × 16-bit × 8 banks, 667M, CL9 Micron MT41J64M16LA-15E www.micron.com

1 2 ... 56 57 58 59 60 61 62 63 64 65 66 ... 77 78

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