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Bare-Metal Compiler
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2014.12.15
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The bare-metal compiler that is shipped with the SoC EDS is the Mentor Graphics Sourcery
™
CodeBench
Lite Edition, version 4.9.1. For more information on the Sourcery CodeBench Lite Edition and for
downloading the latest version of the tools, refer to the Mentor Graphics website (www.mentor.com).
The compiler is a GCC-based arm-altera-eabi port. It targets the ARM processor, it assumes bare-metal
operation, and it uses the standard ARM embedded-application binary interface (EABI) conventions.
The bare-metal compiler is installed as part of the SoC EDS installation in the following folder: <SoC EDS
installation directory>/host_tools/mentor/gnu/arm/baremetal.
The Embedded Command Shell, opened by running the script from the SoC EDS installation folder, sets
the correct environment PATH variables for the bare-metal compilation tools to be invoked. After
starting the shell, commands like arm-altera-eabi-gcc can be invoked directly. When the Eclipse environ‐
ment is started from the embedded command shell, it inherits the environment settings, and it can call
these compilation tools directly.
Alternatively, the full path to the compilation tools can be used: <SoC EDS installation directory>/host_tools/
mentor/gnu/arm/baremetal/bin.
The bare-metal compiler comes with full documentation, located at <SoC EDS installation directory>/host_
tools/mentor/gnu/arm/baremetal/share/doc/sourceryg++-arm-altera-eabi. The documentation is offered in four
different formats to accommodate various user preferences:
• Html files
• Info files
• Man pages
• PDF files
Among the provided documents are:
• Compiler manual
• Assembler manual
• Linker manual
• Binutils manual
• GDB manual
• Getting Started Guide
• Libraries Manual
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2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Overview 6
- Device Tree Binary 7
- Related Information 10
- Installation Folders 11
- Installing the SoC EDS 11
- Licensing 13
- Activating the License 14
- 5. Click Next 17
- Jumper Settings 21
- Start Eclipse 25
- Create New Project 25
- Set the Linker Script 28
- Write Application Source Code 31
- Build Application 34
- TestProject.axf executable 35
- Debug Application 36
- Create a New Project 45
- Figure 4-6: New Project 46
- Create a Linker Script 48
- Figure 4-14: Settings 55
- Figure 4-16: New Source File 57
- Figure 4-17: New Source File 58
- Figure 4-19: Build Project 60
- Starting the Eclipse IDE 71
- Application Console 76
- Sequence Sample Application 85
- Function 85
- Used Hardware 85
- Libraries APIs 85
- Description 85
- Debugging the Kernel 92
- Configuring Linux 97
- File Name Description 100
- Altera Corporation 101
- Getting Started Guides 101
- Send Feedback 101
- Figure 4-59: Browse Target 105
- 2014.12.15 108
- Getting Started with Tracing 111
- Figure 4-67: Trace Into ETF 112
- FPGA Triggering HPS Example 119
- HPS Triggering FPGA Example 123
- ARM DS-5 Altera Edition 126
- Bare-metal Project Management 127
- Creating Project 130
- Build Settings 134
- Build > Settings 135
- Creating a Project 136
- Figure 5-10: New Project 137
- Baremetal GCC. Click Finish 138
- Linker Script 140
- + Build > Settings 146
- Debugging 147
- Debug Configuration Options 150
- Connection Options 151
- Files Options 156
- Debugger Options 156
- RTOS Awareness 157
- Arguments 158
- Environment 158
- DTSL Options 159
- Cross Trigger Settings 160
- Trace Buffer Settings 161
- Cortex-A9 Settings 162
- STM Settings 163
- ETR Settings 163
- ETF Settings 164
- Embedded Command Shell 165
- HPS Preloader User Guide 166
- Hardware Handoff Files 168
- Using .tcl Scripts 169
- Option Required Description 171
- BSP Settings 174
- 2013.05.03 175
- Reset Assert Settings 179
- Preloader Compilation 180
- Preloader Image Tool 181
- Tool Usage 183
- Output Image Layout 184
- Hardware Library 188
- Feature Description 189
- Subscribe 191
- HPS Flash Programmer 192
- Option Short 193
- Required Description 193
- Supported Memory Devices 196
- Bare-Metal Compiler 198
- SD Card Boot Utility 199
- Tool Options 200
- Linux Compiler 202
- Device Tree Generator 205
- Yocto Plugin 206
- Support and Feedback 207
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