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BSP Setting Default Value
spl.reset_assert.GPIO1 False
spl.reset_assert.GPIO2 False
spl.reset_assert.L4WD1 False
spl.reset_assert.OSC1TIMER1 False
spl.reset_assert.SDR False
spl.reset_assert.SPTIMER0 False
spl.reset_assert.SPTIMER1 False
Preloader Compilation
The makefile created by the PSP generator compiles the preloader sources and generates a preloader
image. The makefile performs the following tasks:
• Copies the generic preloader source code into <bsp directory>/uboot-socfpga
• Copies the generated BSP files and hardware handoff files to the source directory in <bsp_directory>/
uboot-socfpga/board/altera/socfpga_<device>
• Configures the compiler tools to target an SoC FPGA
• Compiles the source files in <bsp directory>/uboot-socfpga with the user-specified cross compiler
(specified in the BSP settings) and stores the generated preloader binary files in <bsp_directory>/uboot-
socfpga/spl
• Converts the preloader binary file to a preloader image, <bsp_directory>/preloader-mkpimage.bin, with
the mkpimage tool
The mkpimage tool is part of the SoC EDS. It inserts the correct header information and creates an Altera
boot-ROM compatible image of the preloader. You can run the make utility in the command shell to
compile the preloader in the BSP directory. The makefile contains the following targets:
• make all – compiles the preloader
• make clean – deletes preloader-mkpimage.bin from the <bsp directory>
• make clean-all – deletes <bsp directory>, including the source files in the directory
Related Information
Preloader Image Tool on page 7-16
Configuring FPGA from Preloader
The Preloader has the ability to configure the FPGA by using configuration data stored in one of the
following two locations:
• specific address in QSPI Flash
• specific file name on a SD/MMC FAT Partition
In order to configure the FPGA, an RBF file needs to be used. The RBF file is obtained by converting a
SOF file to RBF by using the Quartus II Programmer.
ug-1137
2013.05.03
Preloader Compilation
7-15
HPS Preloader User Guide
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Overview 6
- Device Tree Binary 7
- Related Information 10
- Installation Folders 11
- Installing the SoC EDS 11
- Licensing 13
- Activating the License 14
- 5. Click Next 17
- Jumper Settings 21
- Start Eclipse 25
- Create New Project 25
- Set the Linker Script 28
- Write Application Source Code 31
- Build Application 34
- TestProject.axf executable 35
- Debug Application 36
- Create a New Project 45
- Figure 4-6: New Project 46
- Create a Linker Script 48
- Figure 4-14: Settings 55
- Figure 4-16: New Source File 57
- Figure 4-17: New Source File 58
- Figure 4-19: Build Project 60
- Starting the Eclipse IDE 71
- Application Console 76
- Sequence Sample Application 85
- Function 85
- Used Hardware 85
- Libraries APIs 85
- Description 85
- Debugging the Kernel 92
- Configuring Linux 97
- File Name Description 100
- Altera Corporation 101
- Getting Started Guides 101
- Send Feedback 101
- Figure 4-59: Browse Target 105
- 2014.12.15 108
- Getting Started with Tracing 111
- Figure 4-67: Trace Into ETF 112
- FPGA Triggering HPS Example 119
- HPS Triggering FPGA Example 123
- ARM DS-5 Altera Edition 126
- Bare-metal Project Management 127
- Creating Project 130
- Build Settings 134
- Build > Settings 135
- Creating a Project 136
- Figure 5-10: New Project 137
- Baremetal GCC. Click Finish 138
- Linker Script 140
- + Build > Settings 146
- Debugging 147
- Debug Configuration Options 150
- Connection Options 151
- Files Options 156
- Debugger Options 156
- RTOS Awareness 157
- Arguments 158
- Environment 158
- DTSL Options 159
- Cross Trigger Settings 160
- Trace Buffer Settings 161
- Cortex-A9 Settings 162
- STM Settings 163
- ETR Settings 163
- ETF Settings 164
- Embedded Command Shell 165
- HPS Preloader User Guide 166
- Hardware Handoff Files 168
- Using .tcl Scripts 169
- Option Required Description 171
- BSP Settings 174
- 2013.05.03 175
- Reset Assert Settings 179
- Preloader Compilation 180
- Preloader Image Tool 181
- Tool Usage 183
- Output Image Layout 184
- Hardware Library 188
- Feature Description 189
- Subscribe 191
- HPS Flash Programmer 192
- Option Short 193
- Required Description 193
- Supported Memory Devices 196
- Bare-Metal Compiler 198
- SD Card Boot Utility 199
- Tool Options 200
- Linux Compiler 202
- Device Tree Generator 205
- Yocto Plugin 206
- Support and Feedback 207
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