Altera POS-PHY Level 2 and 3 Compiler Manuale Utente Scaricare il pdf (Pagina 25)

Chapter 2: Getting Started 2–13

Simulate the Design

Preliminary

IP Functional Simulation Model

This section tells you how to use the demonstration testbench with the ModelSim

simulator or with other simulators using NativeLink.

f For more information on NativeLink, refer to the Simulating Altera IP in Third-Party

Simulation Tools chapter in volume 3 of the Quartus II Handbook.

Testbench with the ModelSim Simulator

To use an example testbench with IP functional simulation models in the ModelSim

simulator, follow these steps:

1 The testbench includes pregenerated Verilog HDL IP functional simulation models.

1. Start the ModelSim simulator.

2. Change the directory to the sim_lib\modelsim directory.

3. For VHDL type the following command:

do compile_pl3_link_source_fixed_example_vlog_ipfs.tclr

or for Verilog HDL type the following command:

do compile_pl3_link_source_fixed_example_vhdl_ipfs.tclr

1 For the sink example, replace source with sink.

Testbench with NativeLink

You can run receive and transmit tests with third-party IP functional simulators using

NativeLink, for VHDL or Verilog HDL. The following procedure describes a receive

test for the Verilog HDL model.

To use the testbench with NativeLink, follow these steps:

1. Using the New Project Wizard in the Quartus II software, create a new project in

the \posphy_l2_l3\sim_lib\testbench\verilog directory with the project name

and top-level entity name of auk_pac_mrx_pl3_link.

1 For the VHDL model, replace the verilog directory with the vhdl directory.

1 For the transmit test, replace mrx with mtx.

2. Add the POS-PHY level 2 and 3 library:

a. On the Assignments menu click Settings.

b. Under Category click Libraries

c. In Project library name click ...

d. Browse to \pos_phy_l2l3\lib and click Open.

e. Click Add.

f. Click OK.

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Altera POS-PHY Level 2 and 3 Compiler Manuale Utente Pagina 25