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SystemVerilog API Overview
Operational Transaction Fields
Mentor Verification IP AE AXI4-Lite User Guide, V10.3
37
April 2014
VALID Signal Delay Transaction Fields
The transaction record contains a *_valid_delay transaction field for each of the five protocol
channels to configure the delay value prior to the assertion of the *VALID signal for the
channel. The master BFM holds the delay configuration for the *VALID signals that it asserts,
and the slave BFM holds the delay configuration for the *VALID signals that it asserts.
Table 2-2 specifies which *_valid_delay fields are configured by the master and slave BFMs.
*READY Handshake Signal Delay Transaction Fields
The transaction record contains a *_ready_delay transaction field for each of the five protocol
channels to store the delay value that occurred between the assertion of the *VALID and
*READY handshake signals for the channel. Table 2-3 specifies the *_ready_delay field
corresponding to the *READY signal delay.
Transaction Done
The transaction_done field in each transaction indicates when the transaction is complete.
In a master BFM test program, you call the get_read_data_phase() task to investigate whether a
read transaction is complete, and the get_write_response_phase() to investigate whether a write
transaction is complete.
Table 2-2. Master and Slave *_valid_delay Configuration Fields
Signal Operational Transaction Field Configuration BFM
AWVALID address_valid_delay Master
WVALID data_valid_delay Master
BVALID write_response_valid_delay Slave
ARVALID address_valid_delay Master
RVALID data_valid_delay Slave
Table 2-3. Master and Slave *_ready_delay Transaction Fields
Signal Operational Transaction Field
AWREADY address_ready_delay
WREADY data_ready_delay
BREADY write_response_ready_delay
ARREADY address_ready_delay
RREADY data_ready_delay
- AMBA AXI4-Lite 1
- User Guide 1
- Table of Contents 10
- List of Examples 12
- List of Figures 14
- List of Tables 15
- About This User Guide 17
- Protocol Restrictions 17
- Supported Simulators 18
- Simulator GCC Requirements 18
- Chapter 1 21
- Mentor VIP Altera Edition 21
- What Is a Transaction? 22
- AXI4-Lite Transactions 22
- Chapter 2 27
- SystemVerilog API Overview 27
- Chapter 3 39
- SystemVerilog Master BFM 39
- SystemVerilog Master API 43
- Returns 44
- Example 58
- Chapter 4 63
- SystemVerilog Slave BFM 63
- SystemVerilog Slave API 68
- Arguments config_name 69
- Chapter 5 91
- SystemVerilog Monitor API 96
- Prototype 100
- Arguments 100
- April 2014 102
- SystemVerilog Monitor BFM 105
- Helper Functions 111
- SystemVerilog Tutorials 115
- Chapter 6 115
- BFM Master Test Program 116
- Verifying a Slave DUT 117
- Verifying a Master DUT 123
- Basic Slave API Definition 124
- *_valid_delay = 4 127
- *_ready_delay = 2 127
- Advanced Slave API Definition 129
- Initial Block 131
- Chapter 7 137
- VHDL API Overview 137
- Test Program VHDL 138
- Configuration 139
- Creating Transactions 139
- Transaction Definition 140
- Executing Transactions 144
- Waiting Events 145
- Access Transaction Record 146
- Operation Mode 147
- Channel Handshake Delay 147
- Handshake Delay 148
- Transaction Done 149
- Chapter 8 151
- VHDL Master BFM 151
- Master BFM Protocol Support 152
- Master Timing and Events 152
- Master BFM Configuration 152
- Master Assertions 155
- VHDL Master API 156
- Chapter 9 213
- VHDL Slave BFM 213
- Slave BFM Configuration 214
- Slave Assertions 216
- VHDL Slave API 217
- Operational 223
- Transaction 223
- Chapter 10 279
- VHDL Monitor BFM 279
- Monitor BFM Configuration 280
- Monitor Assertions 282
- VHDL Monitor API 283
- Chapter 11 335
- VHDL Tutorials 335
- BFM Slave Test Program 341
- Chapter 12 353
- Running the Qsys Tool 356
- Running a Simulation 359
- ModelSim Simulation 360
- Editing the modelsim.ini File 363
- Questa Simulation 364
- Cadence IES Simulation 364
- Synopsys VCS Simulation 366
- Appendix A 369
- AXI4-Lite Assertions 384
- Appendix B 385
- SystemVerilog Test Programs 385
- Appendix C 397
- VHDL Test Programs 397
- End-User License Agreement 409
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