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SystemVerilog Tutorials
Verifying a Master DUT
Mentor Verification IP AE AXI4-Lite User Guide, V10.3
129
April 2014
Advanced Slave API Definition
Note
You are not required to edit the following Advance Slave API unless you require a
different response than the default (OKAY) response.
The remaining section of this tutorial presents a walk-through of the Advanced Slave API in the
slave test program. It consists of four main tasks: process_read(), process_write(),
handle_read(), and handle_write() in the slave test program, as shown in Figure 6-7. There are
additional handle_write_addr_ready(), handle_read_addr_ready() and
handle_write_data_ready() tasks to handle the handshake AWREADY, ARREADY and
WREADY signals, respectively.
The Advanced Slave API is capable of handling pipelined transactions. Pipelining can occur
when a transaction starts before a previous transaction has completed. Therefore, a write
transaction that starts before a previous write transaction has completed can be pipelined.
Figure 6-7 shows the write channel with three concurrent write_trans transactions, whereby the
get_write_addr_phase[2], get_write_data_phase[1], and execute_write_response_phase[0] are
concurrently active on the write address, data, and response channels, respectively.
Similarly, a read transaction that starts before a previous read transaction has completed can be
pipelined. Figure 6-7 shows the read channel with two concurrent read_trans transactions,
whereby the get_read_addr_phase[1] and execute_read_data_phase[0] are concurrently active
on the read address and data channels, respectively.
- AMBA AXI4-Lite 1
- User Guide 1
- Table of Contents 10
- List of Examples 12
- List of Figures 14
- List of Tables 15
- About This User Guide 17
- Protocol Restrictions 17
- Supported Simulators 18
- Simulator GCC Requirements 18
- Chapter 1 21
- Mentor VIP Altera Edition 21
- What Is a Transaction? 22
- AXI4-Lite Transactions 22
- Chapter 2 27
- SystemVerilog API Overview 27
- Chapter 3 39
- SystemVerilog Master BFM 39
- SystemVerilog Master API 43
- Returns 44
- Example 58
- Chapter 4 63
- SystemVerilog Slave BFM 63
- SystemVerilog Slave API 68
- Arguments config_name 69
- Chapter 5 91
- SystemVerilog Monitor API 96
- Prototype 100
- Arguments 100
- April 2014 102
- SystemVerilog Monitor BFM 105
- Helper Functions 111
- SystemVerilog Tutorials 115
- Chapter 6 115
- BFM Master Test Program 116
- Verifying a Slave DUT 117
- Verifying a Master DUT 123
- Basic Slave API Definition 124
- *_valid_delay = 4 127
- *_ready_delay = 2 127
- Advanced Slave API Definition 129
- Initial Block 131
- Chapter 7 137
- VHDL API Overview 137
- Test Program VHDL 138
- Configuration 139
- Creating Transactions 139
- Transaction Definition 140
- Executing Transactions 144
- Waiting Events 145
- Access Transaction Record 146
- Operation Mode 147
- Channel Handshake Delay 147
- Handshake Delay 148
- Transaction Done 149
- Chapter 8 151
- VHDL Master BFM 151
- Master BFM Protocol Support 152
- Master Timing and Events 152
- Master BFM Configuration 152
- Master Assertions 155
- VHDL Master API 156
- Chapter 9 213
- VHDL Slave BFM 213
- Slave BFM Configuration 214
- Slave Assertions 216
- VHDL Slave API 217
- Operational 223
- Transaction 223
- Chapter 10 279
- VHDL Monitor BFM 279
- Monitor BFM Configuration 280
- Monitor Assertions 282
- VHDL Monitor API 283
- Chapter 11 335
- VHDL Tutorials 335
- BFM Slave Test Program 341
- Chapter 12 353
- Running the Qsys Tool 356
- Running a Simulation 359
- ModelSim Simulation 360
- Editing the modelsim.ini File 363
- Questa Simulation 364
- Cadence IES Simulation 364
- Synopsys VCS Simulation 366
- Appendix A 369
- AXI4-Lite Assertions 384
- Appendix B 385
- SystemVerilog Test Programs 385
- Appendix C 397
- VHDL Test Programs 397
- End-User License Agreement 409
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