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Signal Required Description

full

When asserted, the FIFO IP core is considered full. Do not perform

write request operation when the FIFO IP core is full. In general, the

rdfull signal is a delayed version of the wrfull signal. However, the

rdfull signal functions as a combinational output instead of a

derived version of the wrfull signal. Therefore, you must always

refer to the wrfull port to ensure whether or not a valid write

request operation can be performed, regardless of the target device.

wrfull

rdfull

empty

When asserted, the FIFO IP core is considered empty. Do not

perform read request operation when the FIFO IP core is empty. In

general, the wrempty signal is a delayed version of the rdempty

signal. However, the wrempty signal functions as a combinational

output instead of a derived version of the rdempty signal. Therefore,

you must always refer to the rdempty port to ensure whether or not a

valid read request operation can be performed, regardless of the

target device.

wrempty

rdempty

almost_full No Asserted when the usedw signal is greater than or equal to the

Almost full parameter. It is used as an early indication of the full

signal.

almost_empty No Asserted when the usedw signal is less than the Almost empty

parameter. It is used as an early indication of the empty signal.

usedw

Show the number of words stored in the FIFO. Ensure that the port

width is equal to the usedw[] parameter if you manually instantiate

the FIFO IP core in SCFIFO or DCFIFO modes. In DCFIFO_

MIXED_WIDTH mode, the width of the wrusedw and rdusedw ports

must be equal to the usedw[] and Use a different output width

parameters respectively.

wrusedw

rdusedw

FIFO IP Core Parameters for MAX 10 Devices

Table 9-3: FIFO IP Core Parameters for MAX 10 Devices

This table lists the IP core parameters applicable to MAX 10 devices.

Parameter HDL Parameter Description

How wide should the

FIFO be?

lpm_width Specifies the width of the data and q ports for the FIFO IP

core in SCFIFO mode and DCFIFO mode. For the FIFO IP

core in DCFIFO_MIXED_WIDTHS mode, this parameter

specifies only the width of the data port.

Use a different output

width

(1)

lpm_width_r Specifies the width of the q port for the FIFO IP core in

DCFIFO_MIXED_WIDTHS mode.

(1)

Applicable in DCFIFO_MIXED_WIDTHS mode only.

9-4

FIFO IP Core Parameters for MAX 10 Devices

UG-M10MEMORY

2015.05.04

Altera Corporation

FIFO IP Core References

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