Altera Internal Memory (RAM and ROM) IP Core Manuale Utente Scaricare il pdf (Pagina 52)

Figure 5-2: Same-Port Read-During-Write

This figure shows the timing diagram of when the same-port read-during-write occurs for each port A

and port B of the RAM.

At 2500 ps, same-port read-during-write occurs for each port A and port B. Because the true dual-port

RAM configured to port A is reading the new data and port B is reading the old data when the same-port

read-during-write occurs, the rdata1 port shows the new data aa and the rdata2 port shows the old data

00 after four clock cycles at 17500 ps. When the data is read again from the same address at the next rising

clock edge at 7500 ps, the rdata2 port shows the recent data bb at 22500 ps.

5-6

Simulation Results

UG-01068

2014.12.17

Altera Corporation

Design Example

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Altera Internal Memory (RAM and ROM) IP Core Manuale Utente Pagina 52