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Chapter 3: Functional Description—ALTMEMPHY (nonAFI) 3–43
Design Considerations
© January 2010 Altera Corporation External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide
Handshake Mechanism Between Read Commands and Read Data
The controller generates a signal (ctl_doing_rd) to the ALTMEMPHY
megafunction which is asserted for one phy_clk cycle for every read command it
issues. If there are two read commands, the signal ctl_doing_rd is asserted for two
phy_clk cycles. This signal also enables the capture registers and generates the
ctl_mem_rdata_valid signal. This signal should be issued at the same time the
read command is sent to the ALTMEMPHY megafunction (refer to Figure 3–12).
1 The signals under the PHY Command Input label are the signals from the controller to
the ALTMEMPHY megafunction. The signals under the PHY Command Output label
are the signals coming out of the ALTMEMPHY megafunction and input to the
memory device.
Figure 3–12. Read Commands and Read Data (Half-Rate Controller)
Notes to Figure 3–12:
(1) The DDR command shows the command comprised of the command signals (ctl_mem_ras_n_h, ctl_mem_cas_n_h, and
ctl_mem_we_n_h) seen at the ALTMEMPHY input. There can be more than one clock cycle of no operation (NOP) between active (ACT) to
RD depending on the value of t
RCD
parameter of your memory device.
(2) The DDR command shows the command comprised of the command signals (mem_ras_n_h, mem_cas_n_h and mem_we_n_h) seen at
the memory interface. There can be more than one clock cycle of NOP between active ACT to RD depending on the value of the t
RCD
parameter of
your memory device.
phy_clk
ctl_mem_addr_h
ctl_mem_cs_h
ctl_mem_odt_h
DDR Command
(1)
mem_clk
mem_addr
mem_odt
mem_dqs
mem_dq
ctl_mem_rdata
ctl_doing_rd
ctl_mem_rdata_valid
DDR Command
(2)
mem_cs_n
2818967...
503031e...
1
2
4
5
PHY Command Input
PHY Read Data Input
PHY Command Output
Memory Interface
PHY Read Data Output
2
3
4
NOP NOP NOP NOPRD RDPCH ACT NOP
0000 0004 0008 000C 0010 0000
PCH NOP NOP NOP NOP ACTPCHRDACT
0000 0000 000C 000000100004 00080002
23eaf1c823eaf1c8 46c9ff8d...
8c8fe30...
0503db0...
0a06ab1...
140c4b3...
140c4b38140c4b38
- 1
- Contents 3
- 1. About this Megafunction 5
- 2. Parameter Settings 7
- Memory Settings 8
- QDR II+/QDR II SRAM 9
- Note to Table 2–3: 12
- Note to Table 2–5: 13
- Emulated Device 14
- Actual Device 14
- Figure 2–4. Preset Editor 15
- (nonAFI) 17
- PHY-to-Controller Interfaces 20
- Initialization Timing 21
- Note to Figure 3–5: 23
- ALTMEMPHY Signals 25
- Notes to Table 3–1: 26
- Note to Table 3–2: 27
- Notes to Table 3–5: 28
- Note to Table 3–6: 31
- Note to Table 3–7: 33
- Note to Table 3–8: 35
- QDR II+/QDR II SRAM Signals 36
- Note to Table 3–11: 37
- Note to Table 3–14: 39
- Note to Table 3–15: 39
- Understanding the Testbench 41
- Functional Memory Use 42
- Figure 3–6. Example Testbench 44
- Initialization Stage 45
- Write Training Data Stage 47
- Read Calibration Phase 49
- Functional Memory Use Stage 53
- Additional Debug Signals 55
- Calibration Status Interface 56
- Design Considerations 57
- Local Interface Requirements 58
- Notes to Figure 3–12: 59
- Notes to Figure 3–13: 61
- Notes to Figure 3–14: 64
- Notes to Figure 3–15: 66
- DDR2/DDR SDRAM 69
- Clock and Reset Management 71
- Stratix II GX devices use 73
- Notes to Table 4–1: 74
- Write Datapath 76
- Address and Command Datapath 77
- ), write_clk_2x (270), or 78
- Full-Rate Support 79
- Additional Information 81
- How to Contact Altera 82
- Typographic Conventions 82
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