Altera Arria V Hard IP for PCI Express manuali

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Altera Arria V Hard IP for PCI Express Manuale Utente (288 pagine)

Marchio: Altera | Categoria: Strumenti di misura | Dimensione: 5.64 MB |

Indice

User Guide

Contents

Chapter 7. IP Core Interfaces

Chapter 9. Reset and Clocks

Chapter 18. Debugging

1. Datasheet

1–2 Chapter 1: Datasheet

Features

Notes to Table 1–1:

Release Information

Device Family Support

Configurations

Debug Features

IP Core Verification

Recommended Speed Grades

1–8 Chapter 1: Datasheet

Qsys Design Flow

Generating the Testbench

Modifying the Example Design

Running Qsys

Table 3–5

On Chip r

Simulating the Example Design

Direct BFM’s shared memory

{*reconfig_xcvr_clk*}

Compiling the Design

Programming a Device

System Settings

Port Functions

Error Reporting

31 19 18 17 16 15 14

Power Management

Legacy Interrupt

Base Address Registers

PCI Express/PCI Capabilities

Header

6. IP Core Architecture

Avalon-ST Interface

RX Datapath

TX Datapath

Altera FPGA

Clocks and Reset

Interrupts

Transaction Layer

Protocol Layers

Configuration Space

Data Link Layer

Figure 6–4. Data Link Layer

Physical Layer

Figure 6–5. Physical Layer

Multi-Function Support

PCI Express Avalon-MM Bridge

Avalon-MM Bridge TLPs

Figure 6–9. Poor Address Map

RX Block

Avalon-MM RX Master Block

TX Block

Interrupt Handler Block

7. IP Core Interfaces

Note to Table 7–1:

100

RX Port

101

Avalon-ST RX Interface

103

Note to Figure 7–7:

108

Avalon-ST TX Interface

113

Note to Table 7–4:

116

ECRC Forwarding

121

Clock Signals

121

Reset Signals

122

and the LTSSM L0 state

124

ECC Error Signals

125

Interrupts for Endpoints

125

Interrupts for Root Ports

126

Completion Side Band Signals

126

Specification, Rev. 2.1

128

D E F 0 1 2 3

131

Notes to Table 7–13:

132

LMI Signals

136

LMI Read Operation

137

LMI Write Operation

137

Power Management Signals

138

(Full-Featured Qsys)

140

Completer-Only Single DWord

141

RX Avalon-MM Master Signals

143

Transceiver Reconfiguration

145

Serial Interface Signals

145

PIPE Interface Signals

149

Test Signals

153

Notes to Table 7–27:

154

8. Register Descriptions

155

Note to Table 8–2:

156

Note to Table 8–3:

157

Note to Table 8–4:

157

Note to Table 8–5:

157

Note to Table 8–6:

158

Note to Table 8–7:

158

Note to Table 8–8:

159

PCI Express Mailbox Registers

167

Note to Table 8–30:

168

Root Port TLP Data Registers

170

Sending a TLP

173

Receiving a Completion TLP

173

Endpoints

174

Avalon-MM Mailbox Registers

175

Spec 2.1

176

9. Reset and Clocks

181

Example Design

182

Hard IP for PCI Express

182

127 cycles

184

±300 PPM

185

Note to Table 9–2:

186

Transceiver Clock Signals

187

Supported Message Types

189

Notes to Table 10–1:

191

Receive Buffer Reordering

192

Notes to Table 10–2:

193

MSI Interrupts

195

11–2 Chapter 11: Interrupts

196

Note to Figure 11–4:

197

Legacy Interrupts

198

Application Layer

199

11–6 Chapter 11: Interrupts

200

MSI/MSI-X Support

201

Qsys System

202

12. Optional Features

203

ECRC on the RX Path

204

ECRC on the TX Path

205

13. Flow Control

207

13–2 Chapter 13: Flow Control

208

Throughput of Posted Writes

208

Chapter 13: Flow Control 13–3

209

13–4 Chapter 13: Flow Control

210

14. Error Handling

211

Physical Layer Errors

212

Data Link Layer Errors

212

Transaction Layer Errors

213

Note to Table 14–4:

215

Figure 15–2

218

Core User Guide

219

16. SDC Timing Constraints

221

Endpoint Testbench

224

Root Port Testbench

225

Chaining DMA Design Examples

226

Root Complex

227

Chaining DMA

227

Hard IP for

227

PCI Express

227

Note to Table 17–2:

232

Note to Table 17–4:

233

Test Driver Module

236

DMA Write Cycles

237

DMA Read Cycles

239

Root Port Design Example

240

Root Port

241

Variation

241

(variation_name.v)

241

Root Port BFM

242

BFM Memory Map

244

Figure 17–6

248

BFM Read and Write Procedures

250

BFM Procedures and Functions

251

BFM Configuration Procedures

256

Shared Memory Constants

257

18. Debugging

271

18–2 Chapter 18: Debugging

272

Link Training

272

Chapter 18: Debugging 18–3

273

18–4 Chapter 18: Debugging

274

Chapter 18: Debugging 18–5

275

Setting Up Simulation

276

Chapter 18: Debugging 18–7

277

Use Third-Party PCIe Analyzer

278

BIOS Enumeration Issues

278

Notes to Table A–7:

280

Chapter : A–3

281

Notes to Table A–16:

282

Additional Information

283

Info–2 Revision History

284

How to Contact Altera

285

Typographic Conventions

286

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Altera Arria V Hard IP for PCI Express manuali

Altera Arria V Hard IP for PCI Express Manuale Utente (288 pagine)

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