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Figure 8-3: ALTFP_SQRT Signals

data[]

clock

clk_en

inst

ALTFP_SQRT

result[]

overflow

nan

zero

aclr

Table 8-4: ALTFP_SQRT IP Core Input Signals

Port Name Required Description

clock Yes Clock input to the IP core.

clk_en No Clock enable that allows square root operations when the port is

asserted high. When the port is asserted low, no operation occurs and

the outputs remain unchanged.

aclr No Asynchronous clear. When the aclr port is asserted high, the function

is asynchronously reset.

Yes Floating-point input data. The MSB is the sign, the next MSBs are the

exponent, and the LSBs are the mantissa. This input port size is the

total width of sign bit, exponent bits, and mantissa bits.

Table 8-5: ALTFP_SQRT IP Core Output Signals

Port Name Required Description

result[] Yes Square root output port for the floating-point result. The MSB is the

sign, the next MSBs are the exponent, and the LSBs are the mantissa.

The size of this port is the total width of the sign bit, exponent bits,

and mantissa bits.

overflow Yes Overflow port. Asserted when the result of the square root (after

rounding) exceeds or reaches infinity. Infinity is defined as a number

in which the exponent exceeds 2

WIDTH_EXP

-1.

zero Yes Zero port. Asserted when the value of the result[] port is 0.

nan Yes NaN port. Asserted when an invalid square root occurs, such as

negative numbers or NaN inputs.

UG-01058

2014.12.19

ALTFP_SQRT Signals

8-5

ALTFP_SQRT

Altera Corporation

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