
ALTERA_FP_FUNCTIONS Signals
Figure 18-1: ALTERA_FP_FUNCTIONS Signals
clk
b (1), (2)
ALTERA_FP_FUNCTIONS
q (1)
a (1)
areset
1) The floating point and fixed point data widths determine the port width of this port.
2) This port is not relevant for convert and square root functions.
Table 18-6: ALTERA_FP_FUNCTIONS Input Signals
Port Name Required Description
clk Yes All input signals must be synchronous to this clock.
areset Yes Asynchronous active-high reset. Deassert this signal synchronously to
the input clock to avoid metastability issues.
en No Global enable signal. This signal is optional.
a Yes Data input signal.
b Yes Data input signal (where applicable).
s Yes Select port for Add/Sub function.
c Yes Data port for integer exponent port for LDExp function.
Table 18-7: ALTERA_FP_FUNCTIONS Output Signals
Port Name Required Description
q Yes Data output signal.
18-24
ALTERA_FP_FUNCTIONS Signals
UG-01058
2014.12.19
Altera Corporation
ALTERA_FP_FUNCTIONS IP Core
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