Altera DE2-70 Manuale Utente Pagina 1

Altera DE2 Board DE2 Development and Education Board User Manual Version 1.41 Copyright © 2007 Altera Corporation

DE2 User Manual 7 SRAM • 512-Kbyte Static RAM memory chip • Organized as 256K x 16 bits • Accessible as memory for the Nios II processor and b

DE2 User Manual 8 Audio CODEC • Wolfson WM8731 24-bit sigma-delta audio CODEC • Line-level input, line-level output, and microphone input jacks

DE2 User Manual 9 Serial ports • One RS-232 port • One PS/2 port • DB-9 serial connector for the RS-232 port • PS/2 connector for connecting

DE2 User Manual 10 At this point you should observe the following: • All user LEDs are flashing • All 7-segment displays are cycling through t

DE2 User Manual 11 Chapter 3 DE2 Control Panel The DE2 board comes with a Control Panel facility that allows a user to access various components

DE2 User Manual 12 7. The Control Panel is now ready for use; experiment by setting the value of some 7-segment display and observing the result

DE2 User Manual 13 Figure 3.3. The DE2 Control Panel concept. The DE2 Control Panel can be used to change the values displayed on 7-segment

DE2 User Manual 14 Figure 3.4. Controlling LEDs and the LCD display. 3.3 SDRAM/SRAM Controller and Programmer The Control Panel can be used

DE2 User Manual 15 A 16-bit word can be written into the SDRAM by entering the address of the desired location, specifying the dat

DE2 User Manual 16 3.4 Flash Memory Programmer The Control Panel can be used to write/read data to/from the Flash memory chip on the DE2 board.

Altera DE2 Board ii CONTENTS Chapter 1 DE2 Package...

DE2 User Manual 17 2. Enter the desired address into the Address box and the data byte into the wDATA box. Then, click on the Write button. To

DE2 User Manual 18 II chip. The connection between the Audio DAC Controller and a lookup table in the FPGA is used to produce a test audio signal

DE2 User Manual 19 3.6 TOOLS – Multi-Port SRAM/SDRAM/Flash Controller The TOOLS page of the Control Panel GUI allows selection of the User Ports

DE2 User Manual 20 AUDIO_DAC Verilog module defines a circuit that reads the contents of the Flash memory and sends it to the external audio chip

DE2 User Manual 21 • Select the TOOLS page and choose Asynchronous 1 for the SRAM multiplexer port as shown in Figure 3.10. Click on the Configu

DE2 User Manual 22 Figure 3.12. A displayed image. You can display any image file by loading it into the SRAM chip or into an M4K memory blo

DE2 User Manual 23 Figure 3.13. The image converter window. Image Source R/G/B Band Filter B&W Threshold Filter Output Result (640

DE2 User Manual 24 Chapter 4 Using the DE2 Board This chapter gives instructions for using the DE2 board and describes each of its I/O devices.

DE2 User Manual 25 Configuring the FPGA in JTAG Mode Figure 4.1 illustrates the JTAG configuration setup. To download a configuration bit stream

DE2 User Manual 26 Figure 4.2. The AS configuration scheme. In addition to its use for JTAG and AS programming, the USB Blaster port on the DE

Altera DE2 Board iii 5.2 TV Box Demonstration...

DE2 User Manual 27 There are 27 user-controllable LEDs on the DE2 board. Eighteen red LEDs are situated above the 18 toggle switches, and eight g

DE2 User Manual 28 Figure 4.5. Schematic diagram of the LEDs. Signal Name FPGA Pin No. Description SW[0] PIN_N25 Toggle Switch[0] SW[1] PI

DE2 User Manual 29 Signal Name FPGA Pin No. Description KEY[0] PIN_G26 Pushbutton[0] KEY[1] PIN_N23 Pushbutton[1] KEY[2] PIN_P23 Pushbutto

DE2 User Manual 30 4.3 Using the 7-segment Displays The DE2 Board has eight 7-segment displays. These displays are arranged into two pai

DE2 User Manual 31 Signal Name FPGA Pin No. Description HEX0[0] PIN_AF10 Seven Segment Digit 0[0] HEX0[1] PIN_AB12 Seven Segment Digit 0[1]

DE2 User Manual 32 HEX5[1] PIN_P6 Seven Segment Digit 5[1] HEX5[2] PIN_P7 Seven Segment Digit 5[2] HEX5[3] PIN_T9 Seven Segment Digit 5[3]

DE2 User Manual 33 Figure 4.8. Schematic diagram of the clock circuit. Signal Name FPGA Pin No. Description CLOCK_27 PIN_D13 27 MHz clock i

DE2 User Manual 34 Figure 4.9. Schematic diagram of the LCD module. Signal Name FPGA Pin No. Description LCD_DATA[0] PIN_J1 LCD Data[0] LCD

DE2 User Manual 35 4.6 Using the Expansion Header The DE2 Board provides two 40-pin expansion headers. Each header connects directly to 36 pins

DE2 User Manual 36 GPIO_0[10] PIN_N18 GPIO Connection 0[10] GPIO_0[11] PIN_P18 GPIO Connection 0[11] GPIO_0[12] PIN_G23 GPIO Connection 0[1

DE2 User Manual 1 Chapter 1 DE2 Package The DE2 package contains all components needed to use the DE2 board in conjunction with a

DE2 User Manual 37 GPIO_1[11] PIN_P24 GPIO Connection 1[11] GPIO_1[12] PIN_R25 GPIO Connection 1[12] GPIO_1[13] PIN_R24 GPIO Connection 1[1

DE2 User Manual 38 Figure 4.11. VGA circuit schematic. The timing specification for VGA synchronization and RGB (red, green, blue) data can

DE2 User Manual 39 Figure 4.12. VGA horizontal timing specification. VGA mode Horizontal Timing Spec Configuration Resolution(HxV) a(us) b(

DE2 User Manual 40 Signal Name FPGA Pin No. Description VGA_R[0] PIN_C8 VGA Red[0] VGA_R[1] PIN_F10 VGA Red[1] VGA_R[2] PIN_G10 VGA Red[2]

DE2 User Manual 41 4.8 Using the 24-bit Audio CODEC The DE2 board provides high-quality 24-bit audio via the Wolfson WM8731 audio CO

DE2 User Manual 42 4.9 RS-232 Serial Port The DE2 board uses the MAX232 transceiver chip and a 9-pin D-SUB connector for RS-232 co

DE2 User Manual 43 Signal Name FPGA Pin No. Description PS2_CLK PIN_D26 PS/2 Clock PS2_DAT PIN_C24 PS/2 Data Table 4.11. PS/2 pin assignm

DE2 User Manual 44 ENET_DATA[5] PIN_A17 DM9000A DATA[5] ENET_DATA[6] PIN_B16 DM9000A DATA[6] ENET_DATA[7] PIN_B15 DM9000A DATA[7] ENET_DATA

DE2 User Manual 45 Figure 4.19. TV Decoder schematic. Signal Name FPGA Pin No. Description TD_DATA[0] PIN_J9 TV Decoder Data[0] TD_DATA[1

DE2 User Manual 46 4.13 Implementing a TV Encoder Although the DE2 board does not include a TV encoder chip, the ADV7123 (10-bit high-spee

DE2 User Manual 2 The DE2 package includes: • DE2 board • USB Cable for FPGA programming and control • CD-ROM containing the DE2 documentation

DE2 User Manual 47 Figure 4.21. USB (ISP1362) host and device schematic. Signal Name FPGA Pin No. Description OTG_ADDR[0] PIN_K7 ISP1362 A

DE2 User Manual 48 OTG_WR_N PIN_G1 ISP1362 Write OTG_RST_N PIN_G5 ISP1362 Reset OTG_INT0 PIN_B3 ISP1362 Interrupt 0 OTG_INT1 PIN_C3 ISP13

DE2 User Manual 49 4.16 Using SDRAM/SRAM/Flash The DE2 board provides an 8-Mbyte SDRAM, 512-Kbyte SRAM, and 4-Mbyte (1-Mbyte on some boards) Fla

DE2 User Manual 50 Figure 4.25. Flash schematic. Signal Name FPGA Pin No. Description DRAM_ADDR[0] PIN_T6 SDRAM Address[0] DRAM_ADDR[1] PI

DE2 User Manual 51 DRAM_DQ[9] PIN_AB2 SDRAM Data[9] DRAM_DQ[10] PIN_AB1 SDRAM Data[10] DRAM_DQ[11] PIN_AA4 SDRAM Data[11] DRAM_DQ[12] PIN_

DE2 User Manual 52 SRAM_ADDR[16] PIN_AB8 SRAM Address[16] SRAM_ADDR[17] PIN_AC8 SRAM Address[17] SRAM_DQ[0] PIN_AD8 SRAM Data[0] SRAM_DQ[1]

DE2 User Manual 53 FL_ADDR[10] PIN_AE17 FLASH Address[10] FL_ADDR[11] PIN_AF17 FLASH Address[11] FL_ADDR[12] PIN_W16 FLASH Address[12] FL_A

DE2 User Manual 54 Chapter 5 Examples of Advanced Demonstrations This chapter provides a number of examples of advanced circuits implemented on

DE2 User Manual 55 • Power on the DE2 board, with the USB cable connected to the USB Blaster port. If necessary (that is, if

DE2 User Manual 56 Internally, the VGA Controller generates data request and odd/even selected signals to the SDRAM Frame Buffer and filed select

DE2 User Manual 3 1.3 Getting Help Here are the addresses where you can get help if you encounter problems: • Altera Corporation 101 Innovatio

DE2 User Manual 57 • Connect the audio output of the DVD player to the line-in port of the DE2 board and connect a speaker to th

DE2 User Manual 58 data stored in the frame buffer with a default image pattern and display the overlapped image on the VGA display. Figure 5.3

DE2 User Manual 59 Figure 5.4 illustrates the setup for this demonstration. Figure 5.4. The setup for the USB paintbrush demonstration. 5.4

DE2 User Manual 60 Figure 5.5. Block diagram of the USB device demonstration. Demonstration Setup, File Locations, and Instructions • Projec

DE2 User Manual 61 Figure 5.6. The setup for the USB device demonstration. 5.5 A Karaoke Machine This demonstration uses the microphone-in, l

DE2 User Manual 62 Demonstration Setup, File Locations, and Instructions • Project directory: DE2_i2sound • Bit stream used: DE2_i2sound.sof or

DE2 User Manual 63 On the transmitting side, the Nios II processor sends 64-byte packets every 0.5 seconds to the DM9000A. After r

DE2 User Manual 64 Figure 5.10. The setup for the Ethernet demonstration. 5.7 SD Card Music Player Many commercial media/audio players use a

DE2 User Manual 65 During operation the Nios II processor will check if the FIFO memory of the Audio DAC Controller becomes full. If the FIFO is

DE2 User Manual 66 Figure 5.12. The setup for the SD music player demonstration. 5.8 Music Synthesizer Demonstration This demonstration shows

DE2 User Manual 4 Chapter 2 Altera DE2 Board This chapter presents the features and design characteristics of the DE2 board. 2.1 Layout and Co

DE2 User Manual 67 Figure 5.13. Block diagram of the Music Synthesizer design Demonstration Setup, File Locations, and Instructions • Proj

DE2 User Manual 68  Switches and Pushbuttons Signal Name Description KEY[0] Reset Circuit KEY[1] Repeat the Demo Music SW[0] OFF: BRASS, ON:

DE2 User Manual 69 Figure 5.14. The Setup of the Music Synthesizer Demonstration. Copyright © 2005 Altera Corporation. All rights

DE2 User Manual 5 • 4-Mbyte Flash memory (1 Mbyte on some boards) • SD Card socket • 4 pushbutton switches • 18 toggle switches • 18 red use

DE2 User Manual 6 Figure 2.2. Block diagram of the DE2 board. Following is more detailed information about the blocks in Figure 2.2: Cyclone I