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The I2C connection and timing
TIdevice
I2C
I2C
EPROM
I2C
controller
TIdevice
I2C
V
DD
Pull-up
resistors
Serialdata(SDA)
Serialclock(SCL)
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Peripheral Architecture
2 Peripheral Architecture
The I2C peripheral consists of the following primary blocks:
• A serial interface: one data pin (SDA) and one clock pin (SCL).
• Data registers to temporarily hold receive data and transmit data traveling between the SDA pin and
the CPU or the DMA2 controller.
• Control and status registers.
• A peripheral data bus interface to enable the CPU and the DMA2 controller to access the I2C
peripheral registers.
• A clock synchronizer to synchronize the I2C input clock (from the processor clock generator) and the
clock on the SCL pin, and to synchronize data transfers with masters of different clock speeds.
• A prescaler to divide down the input clock that is driven to the I2C peripheral.
• A noise filter on each of the two pins, SDA and SCL.
• An arbitrator to handle arbitration between the I2C peripheral (when it is a master) and another master.
• Interrupt generation logic, so that an interrupt can be sent to the CPU.
• DMA event generation logic, so that activity in the DMA2 controller can be synchronized to data
reception and data transmission in the I2C peripheral.
Figure 1 shows the four registers used for transmission and reception. The CPU or the DMA controller
writes data for transmission to ICDXR and reads received data from ICDRR. When the I2C peripheral is
configured as a transmitter, data written to ICDXR is copied to ICXSR and shifted out on the SDA pin one
bit at a time. When the I2C peripheral is configured as a receiver, received data is shifted into ICRSR and
then copied to ICDRR.
2.1 Bus Structure
Figure 1 shows how the I2C peripheral is connected to the I2C bus. The I2C bus is a multi-master bus
that supports a multi-master mode. This allows more than one device capable of controlling the bus that is
connected to it. A unique address recognizes each I2C device. Each I2C device can operate as either
transmitter or receiver, depending on the function of the device. Devices that are connected to the I2C bus
can be considered a master or slave when performing data transfers, in addition to being a transmitter or
receiver.
NOTE: A master device is the device that initiates a data transfer on the bus and generates the
clock signals to permit that transfer. Any device that is addressed by this master is
considered a slave during this transfer.
An example of multiple I2C modules that are connected for a two-way transfer from one device to other
devices is shown in Figure 2.
Figure 2. Multiple I2C Modules Connected
11
SPRUFO1A–September 2009 Inter-Integrated Circuit (I2C) Peripheral
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SDA
SCL
MSB
Acknowledgement
bitfromslave
(No-)Acknowledgement
bitfromreceiver
1 2 7 8
R/W
9
ACK
1 2 8 9
ACK
Slaveaddress
START
condition(S)
STOP
condition(P)
Data
S Slaveaddress R/W ACK
Data
ACK
Data
ACK P
7
n n
1 1 1 1 1 1
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Peripheral Architecture
2.6 Serial Data Formats
Figure 7 shows an example of a data transfer on the I2C-bus. The I2C peripheral supports 2-bit to 8-bit
data values. Figure 7 shows a typical I2C data transfer using (BC = 000 in ICMDR). Each bit put on the
SDA line is equivalent to one pulse on the SCL line. The data is always transferred with the
most-significant bit (MSB) first. The number of data values that can be transmitted or received is
unrestricted; however, in most systems, the transmitter and receiver have agreed upon the number of data
values to transfer before transfer begins.
The I2C peripheral supports the following data formats:
• 7-bit addressing mode.
• 10-bit addressing mode.
• Free data format mode.
Figure 7. I2C Peripheral Data Transfer
2.6.1 7-Bit Addressing Format
In the 7-bit addressing format (Figure 8), the first byte after a START condition (S) consists of a 7-bit slave
address followed by a R/W bit. The R/W bit determines the direction of the data.
• R/W = 0: The master writes (transmits) data to the addressed slave.
• R/W = 1: The master reads (receives) data from the slave.
An extra clock cycle dedicated for acknowledgment (ACK) is inserted after the R/W bit. If the slave inserts
the ACK bit, n bits of data from the transmitter (master or slave, depending on the R/W bit) follow it. n is a
number from 2 to 8 that the bit count (BC) bits of ICMDR determine. The receiver inserts an ACK bit after
the data bits have been transferred.
Write a 0 to the expanded address enable (XA) bit of ICMDR to select the 7-bit addressing format.
Figure 8. I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR)
n = The number of data bits (from 2 to 8) specified by the bit count (BC) field of ICM DR.
2.6.2 10-Bit Addressing Format
The 10-bit addressing format (Figure 9) is like the 7-bit addressing format, but the master sends the slave
address in two separate byte transfers. The first byte consists of 11110b, the two MSBs of the 10-bit slave
address, and R/W = 0 (write). The second byte is the remaining 8 bits of the 10-bit slave address. The
slave must send acknowledgment (ACK) after each of the two byte transfers. Once the master has written
the second byte to the slave, the master can either write data or use a repeated START condition to
change the data direction. (For more information about using 10-bit addressing, see the Philips
Semiconductors I2C-bus specification.)
Write 1 to the XA bit of ICMDR to select the 10-bit addressing format.
15
SPRUFO1A–September 2009 Inter-Integrated Circuit (I2C) Peripheral
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Copyright © 2009, Texas Instruments Incorporated
From TI’s SPRUFO1A.
EECS 452 – Fall 2014 Lecture 5 – Page 124/143 Tuesday – September 16, 2014
- EECS 452 – Lecture 5 1
- Lecture overview 2
- Free eBook 3
- Full Custom, ASIC, FPGA 4
- FPGA organization 6
- Coming down the road (at us) 8
- Cyclone II FPGA layout 10
- Cyclone II logic element 11
- Programmable interconnections 12
- Clock distribution network 13
- DE2-70 RAM 14
- (inc. parity) 15
- (not avail. true dual) 15
- Multipliers 16
- Advantages of an FPGA 17
- ASICs, FPGAs’ competition 18
- Who makes FPGAs? 19
- The Terasic/Altera DE2-70 20
- DE2-70 features 21
- The DE2-70 power on default 22
- DE2-70 reference materials 23
- Definitive resources 24
- Learning SystemVerilog 29
- Comments about standards 32
- Verilog DIY learning links 33
- Some Quartus II resources 35
- Processing a design 36
- Quartus II file extensions 37
- .qsf file comments 38
- DE2-70 .qsf file snippet 39
- DE0-Nano .qsf file snippet 40
- Selecting the I/O standard 41
- .sdc file comments 42
- From my .sdc file 43
- Dealing with a pin conflict 44
- Creating a project 45
- Specifying the FPGA (DE2-70) 46
- Almost ready to go 47
- It remains to . . 48
- Quartus II screen shot 49
- The warning windows 50
- Comments on module structure 52
- An Altera example 54
- Altera’s addsub.v example 55
- Verilog’s numbers 57
- Verilog’s base logic elements 58
- Full Adder 59
- Full Adder — Structural 60
- Verilog’s operators 61
- Verilog’s operators part 1 62
- Verilog’s operators part 2 63
- From IEEE Standard 1800-2009 64
- SystemVerilog’s data types 65
- Full adder — Behavioral 66
- Full adder test 68
- Syntax for looping statements 72
- For loop example 73
- For loop example result 74
- Lab exercise 3 75
- CODEC device used on DE2-70 77
- The WM8731, what and how 78
- DE2-70 schematic, CODEC 79
- DE2-70 CODEC pin assignments 80
- Need a fast D/A? 81
- ALTERA DE2-70 82
- Implementing a DDS sine table 83
- Recompiled and ran 86
- Using QuartusII Megafunctions 87
- Megafunctions continued 88
- Specifying a ROM 89
- More .mif information 91
- From Altera documentation 94
- Overflow lecture material 95
- The FPGA Blinky variations 96
- Blinking an LED 97
- Blinky comments 98
- Blinky using registers 99
- Blinky_D comments 100
- Blinky_state part 1 101
- Blinky_state part 2 102
- Blinky_state comments 103
- Loading Blinky into the FPGA 104
- Making Blinky the default 105
- Restoring the default default 106
- The FPGA breakout board 107
- Bit-serial data transfers 110
- Clock domain crossings 111
- CDC references 112
- Understanding clock domain 113
- Metastability cause 114
- An answer is ? 116
- The SPI protocol 118
- SPI timing example 119
- My DIY SPI timing example 120
- The I2S protocol 121
- I2S timing example 122
- The I2C protocol 123
- The I2C connection and timing 124
- The UART protocol 125
- The UART frame 126
- The FT232R UART/USB breakout 127
- Bit-serial comments 128
- Synchronizer module 129
- The Digilent PMod-DA2 module 130
- The DAC121S101 D/A 131
- How to make the D/A work 132
- Starting simple with the D/A 133
- The Digilent PMod-AD1 module 134
- The ADCS7476 A/D 135
- Comments 136
- From the Amazon web site 137
- FYI: Terasic DE0-Nano 138
- DE0–Nano features 139
- A low cost competitor 141
- Starting a personal library 143
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