Altera Stratix IV E FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 47)

Chapter 2: Board Components 2–39

Components and Interfaces

May 2011 Altera Corporation Stratix IV E FPGA Development Board Reference Manual

J9.21 Transceiver TX bit 2

NC 1.4-V PCML

——

J9.22 Transceiver RX bit 2 — —

J9.23 Transceiver TX bit 2n — —

J9.24 Transceiver RX bit 2n — —

J9.25 Transceiver TX bit 1 — —

J9.26 Transceiver RX bit 1 — —

J9.27 Transceiver TX bit 1n — —

J9.28 Transceiver RX bit 1n — —

J9.29 Transceiver TX bit 0 — —

J9.30 Transceiver RX bit 0 — —

J9.31 Transceiver TX bit 0n — —

J9.32 Transceiver RX bit 0n — —

J9.33 Management serial data

HSMB_SDA

2.5-V

U10 —

J9.34 Management serial clock

HSMB_SCL

M28 —

J9.35 JTAG clock signal

JTAG_TCK

——

J9.36 JTAG mode select signal

JTAG_TMS

——

J9.37 JTAG data output

HSMB_JTAG_TDO

——

J9.38 JTAG data input

HSMB_JTAG_TDI

——

J9.39 Dedicated CMOS clock out

HSMB_CLK_OUT0

N6 —

J9.40 Dedicated CMOS clock in

HSMB_CLK_IN0

B19 —

J9.41 Dedicated CMOS I/O bit 0

HSMB_D0

P7 —

J9.42 Dedicated CMOS I/O bit 1

HSMB_D1

W5 —

J9.43 Dedicated CMOS I/O bit 2

HSMB_D2

N5 —

J9.44 Dedicated CMOS I/O bit 3

HSMB_D3

P8 —

J9.47 LVDS TX bit 0 or CMOS bit 4 HSMB_TX_D_P0

LVDS or 2.5-V

P11 —

J9.48 LVDS RX bit 0 or CMOS bit 5 HSMB_RX_D_P0 R4 —

J9.49 LVDS TX bit 0n or CMOS bit 6 HSMB_TX_D_N0 P10 —

J9.50 LVDS RX bit 0n or CMOS bit 7 HSMB_RX_D_N0 R3 —

J9.53 LVDS TX bit 1 or CMOS bit 8 HSMB_TX_D_P1 T9 —

J9.54 LVDS RX bit 1 or CMOS bit 9 HSMB_RX_D_P1 P4 —

J9.55 LVDS TX bit 1n or CMOS bit 10 HSMB_TX_D_N1 T8 —

J9.56 LVDS RX bit 1n or CMOS bit 11 HSMB_RX_D_N1 P3 —

J9.59 LVDS TX bit 2 or CMOS bit 12 HSMB_TX_D_P2 T7 —

J9.60 LVDS RX bit 2 or CMOS bit 13 HSMB_RX_D_P2 P2 —

J9.61 LVDS TX bit 2n or CMOS bit 14 HSMB_TX_D_N2 U6 —

J9.62 LVDS RX bit 2n or CMOS bit 15 HSMB_RX_D_N2 R1 —

J9.65 LVDS TX bit 3 or CMOS bit 16 HSMB_TX_D_P3 T5 —

J9.66 LVDS RX bit 3 or CMOS bit 17 HSMB_RX_D_P3 N2 —

Table 2–41. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

Description Schematic Signal

Name

I/O Standard

Stratix IV E

Device

Pin Number

Other

Connections

1 2 ... 42 43 44 45 46 47 48 49 50 51 52 ... 71 72

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Altera Stratix IV E FPGA Development Board Manuale Utente Pagina 47

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