Altera Stratix II GX Embedded Gigabit Ethernet MAC/PHY Manuale Utente Scaricare il pdf (Pagina 10)

Stratix II GX Embedded Gigabit Ethernet MAC / PHY

User's Guide

Version 1.0 - October 2005

Core

Configuration

Simulation

Control

Modelsim

Control

Figure 5: Testbuilder Panel

Table 3: Simulation Options

Option Unit Description Default

Number of Frames in RX path Frames

Sets the number of frames that are generated by

the Ethernet frame Generator connected to the

Receive PHY interface.

If set to 0, a Serdes loopback test is performed

with the Core pin loop_ena set to '1'.

5

Number of Frames in TX path Frames

Sets the number of frames that are generated by

the frame Generator connected to the Core

transmit FIFO interface.

5

IPG in RX path Bytes

Sets the inter-packet gap (IGP) used by the

Ethernet Frame generator when generating

frames to the RX PHY interface.

12

Length of first frame Bytes

Defines the payload length of the first frame

generated by the Ethernet and FIFO models.

100

10

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 16 17 18

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