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June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
1. About This MegaCore Function
Interlaken is a high-speed serial communication protocol for chip-to-chip packet
transfers. The Altera
®
Interlaken MegaCore
®
function implements the Interlaken
Protocol Specification, Revision 1.2. It supports specific combinations of number of lanes
from 4 to 20, and lane rates from 3.125 to 10.3125 gigabits per second (Gbps), on
Stratix
®
IV GT devices, and lane rates from 3.125 to 6.375 Gbps on Stratix IV GX
devices, providing raw bandwidth of 12.50 Gbps to 127.50 Gbps.
Interlaken provides low I/O count compared to earlier protocols, supporting
scalability in both number of lanes and lane speed. Other key features include flow
control, low overhead framing, and extensive integrity checking. The Interlaken
MegaCore function incorporates a physical coding sublayer (PCS), a physical media
attachment (PMA), and a media access control (MAC) block. The MegaCore function
transmits and receives Avalon
®
Streaming (Avalon-ST) data on its FPGA fabric
interface.
Figure 1–1 shows an example system implementation.
Features
The Interlaken MegaCore function has the following features:
■ Compliant with the Interlaken Protocol Specification, Rev 1.2
■ Supports 4, 8, 10, 12, and 20 serial lanes in configurations that provide nominal
bandwidths of 20 Gbps, 40 Gbps, and 100 Gbps
■ Supports per-lane data rates of 3.125, 6.25, 6.375, and 10.3125 Gbps using Altera
on-chip high-speed transceivers
Figure 1–1. Typical Interlaken Application
Interlaken
MegaCore
Function
Interlaken
MegaCore
Function
Stratix IV GT
FPGA
Stratix IV GX
FPGA
Memory
Controller
High-Speed
Memory
Ethernet MAC
Interlaken Link
Optical
Module
Swuitch Fabric or Backplane
- User Guide 1
- Interlaken MegaCore Function 1
- Contents 3
- Chapter 5. Signals 4
- Contents v 5
- Features 7
- Device Family Support 8
- MegaCore Verification 9
- Release Information 10
- Installation and Licensing 10
- OpenCore Evaluation 12
- 2. Getting Started 13
- Qsys Design Flow Summary 14
- Qsys Design Flow 16
- Specifying Parameters 17
- Completing the Qsys System 18
- Simulating the System 18
- Specifying Constraints 19
- I/O Standard Constraints 20
- 3. Parameter Settings 23
- Lane Rate 24
- Number of Words in Meta Frame 24
- Exclude Transceiver 24
- Burst Parameters 25
- 4. Functional Description 27
- Architecture Overview 28
- Interfaces Overview 28
- Note to Table 4–1: 29
- Avalon-ST Interface 30
- Clocking and Reset Structure 31
- MAC Clock Verified Frequency 35
- PCS Clock Frequencies 36
- Transmit Path 37
- Receive Path 43
- Channel Filtering Blocks 45
- Packet Regrouper 45
- Calendar and Status Block 46
- Lane Status Block 47
- High-Speed I/O Block 48
- Transceivers 49
- 5. Signals 53
- Exclude transceivers 54
- Chapter 5: Signals 5–3 55
- Note to Table 5–2: 56
- Note to Table 5–3: 56
- Application Interface Signals 57
- Note to Table 5–6: 58
- Chapter 5: Signals 5–7 59
- Note to Table 5–8: 60
- Note to Table 5–9: 61
- Note to Table 5–10: 61
- Note to Table 5–11: 62
- Note to Table 5–12: 62
- Transceiver Banks 63
- Running a Design Example 65
- Setting Up the Design Example 66
- Function 69
- Simulation 73
- Reset Signals 79
- Required Reset Sequence 80
- Additional Information 87
- Typographic Conventions 88
- Visual Cue Meaning 89
- Info–4 Additional Information 90
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