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Chapter 3: Specifications 3–17
HyperTransport MegaCore Function Specification
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
Rx Command/Data Buffer Interfaces
Each HT virtual channel has one Rx command/data interface. These interfaces are
slave source Atlantic interfaces, allowing streaming packets in an easy-to-use
interface.
Rx Command/Data Buffer Interface Signals
Table 3–5 describes the Rx buffer interface signals. Each of these signals has one of the
following three types:
■ Rx response interface (HT MegaCore function signal names prefixed with RxR)
■ Rx posted interface (HT MegaCore function signal names prefixed with RxP)
■ Rx non-posted interface (HT MegaCore function signal names prefixed with
RxNp)
Because each channel uses similar interface signals, they are only described once. Any
channels that have specific differences are noted in Table 3–5.
Table 3–5. Rx Command/Data Buffer Interface Signals (Part 1 of 2)
Signal Name Direction Description
Dat_o[63:0] Output Data bus. This 64-bit bus contains the actual HT command/data information received
from the HT link. This bus has the following constraints:
■ Data received from the link is organized in Atlantic packets.
■ Data is transferred in a little endian format (first byte is in Dat_o[7:0]).
■ The Atlantic packet on the Rx interface contains a command phase followed by zero,
one, or more data phases.
■ During the command phase, Sop_o is asserted to indicate the start of packet. That is,
Sop indicates the start of an Atlantic packet and indicates that Dat_o[63:0]
contains the HT command.
■ The data presented on Dat_o[63:0] is presented with the bytes in the order they
are received from the HT link. Therefore, the first byte received from the HT link in a
command packet is provided on Dat_o[7:0].
■ If the command has no associated data, such as a non-posted read request or
TgtDone response packet, Sop_o and Eop_o are asserted at the same time.
■ You can decode the command bits to determine whether there is data associated with
the command (and how much) while Sop_o is asserted.
Mty_o[2:0] Output Data byte empty. This bus indicates which bytes are invalid on Dat_o[63:0]. Because
HT packets are DWORD aligned, only two valid encodings are used by the
HyperTransport MegaCore function. The following Mty_o signal values are possible:
■ Mty_o = '000', all bytes on Dat_o[63:0] are valid.
■ Mty_o = '100', Dat_o[63:32] are invalid.
Invalid bytes can only be on the last word of a packet. It is illegal to have a non-zero value
for the Mty_o signals for words other than the last word of the packet, even for 32-bit
commands that have data, such as a read response. In this case, when Sop_o is
asserted, Dat_o[63:32] is implicitly invalid. The first data bytes are placed on the
Dat_o bus the cycle after Sop_i. If the 32-bit command does not have data, the
Mty_o signals are set to '100', and Eop_o and Sop_o are asserted.
- User Guide 1
- UG-MCHYPRTRNS-1.12 2
- Contents 3
- Appendix C. Example Design 4
- Additional Information 4
- Release Information 5
- Device Family Support 5
- Introduction 6
- Features 6
- Performance 7
- Notes to Table 1–4: 8
- Notes to Table 1–5: 8
- 2. Getting Started 9
- MegaCore Function Walkthrough 10
- Step 1: Parameterize 13
- Step 2: Set Up Simulation 17
- Figure 2–9. Set Up Simulation 18
- Step 3: Generate 19
- Notes to Table 2–1: 20
- Compile the Design 21
- Simulate the Design 21
- Program a Device 22
- Set Up Licensing 23
- Example Quartus II Project 24
- ■ input_ht_vector.dat 25
- ■ output_ht_vector.dat 25
- ■ input_ui_vector.dat 25
- ■ output_ui_vector.dat 25
- About the Test Vectors 26
- 3. Specifications 27
- HT Systems 28
- HT Flow Control 29
- Physical Interface 30
- Protocol Interface 31
- End-Chain Handler 32
- Rx Claimed Buffers 32
- Tx Buffers 32
- Scheduler 32
- Clocking Options 33
- Shared Rx/Tx Clock 34
- Shared Ref/Tx Clock 34
- Chapter 3: Specifications 3–9 35
- Preliminary 35
- Shared Rx/Tx/Ref Clock 36
- Note to Figure 3–8: 37
- HT Link Rx Signals 42
- HT Link System Signals 42
- HT Link Tx Signals 42
- Notes to Table 3–6: 45
- Notes to Figure 3–10: 46
- Notes to Figure 3–11: 46
- Notes to Figure 3–12: 47
- Notes to Figure 3–13: 47
- Notes to Table 3–8: 51
- Addr[39:8] 52
- Notes to Figure 3–16: 53
- Notes to Figure 3–17: 53
- Notes to Figure 3–18: 54
- User Interface System Signals 55
- Using PLL Resets 55
- CSR Interface Signals 56
- CSR Module 57
- Notes to Table 3–13: 58
- Notes: to Table 3–16: 60
- A. Parameters 67
- Base Address Registers 68
- Advanced Settings 69
- A–4 Appendix A: Parameters 70
- Parameter Lists 70
- Guidelines 71
- C. Example Design 73
- General Description 74
- Typographic Conventions 76
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