Altera DSP Development Kit, Stratix V Edition Manuale Utente Scaricare il pdf (Pagina 45)

Chapter 2: Board Components 2–37

Components and Interfaces

July 2012 Altera Corporation DSP Development Kit, Stratix V Edition

Reference Manual

HSMA_RX_P1

1.4-V PCML AP2 Transceiver receive channel

HSMA_RX_N1

1.4-V PCML AP1 Transceiver receive channel

HSMA_RX_P2

1.4-V PCML AM2 Transceiver receive channel

HSMA_RX_N2

1.4-V PCML AM1 Transceiver receive channel

HSMA_RX_P3

1.4-V PCML AK2 Transceiver receive channel

HSMA_RX_N3

1.4-V PCML AK1 Transceiver receive channel

HSMA_RX_P4

1.4-V PCML AH2 Transceiver receive channel

HSMA_RX_N4

1.4-V PCML AH1 Transceiver receive channel

HSMA_RX_P5

1.4-V PCML AF2 Transceiver receive channel

HSMA_RX_N5

1.4-V PCML AF1 Transceiver receive channel

HSMA_RX_P6

1.4-V PCML AD2 Transceiver receive channel

HSMA_RX_N6

1.4-V PCML AD1 Transceiver receive channel

HSMA_RX_P7

1.4-V PCML AB2 Transceiver receive channel

HSMA_RX_N7

1.4-V PCML AB1 Transceiver receive channel

HSMA_TX_P0

1.4-V PCML AU4 Transceiver transmit channel

HSMA_TX_N0

1.4-V PCML AU3 Transceiver transmit channel

HSMA_TX_P1

1.4-V PCML AN4 Transceiver transmit channel

HSMA_TX_N1

1.4-V PCML AN3 Transceiver transmit channel

HSMA_TX_P2

1.4-V PCML AL4 Transceiver transmit channel

HSMA_TX_N2

1.4-V PCML AL3 Transceiver transmit channel

HSMA_TX_P3

1.4-V PCML AJ4 Transceiver transmit channel

HSMA_TX_N3

1.4-V PCML AJ3 Transceiver transmit channel

HSMA_TX_P4

1.4-V PCML AG4 Transceiver transmit channel

HSMA_TX_N4

1.4-V PCML AG3 Transceiver transmit channel

HSMA_TX_P5

1.4-V PCML AE4 Transceiver transmit channel

HSMA_TX_N5

1.4-V PCML AE3 Transceiver transmit channel

HSMA_TX_P6

1.4-V PCML AC4 Transceiver transmit channel

HSMA_TX_N6

1.4-V PCML AC3 Transceiver transmit channel

HSMA_TX_P7

1.4-V PCML AA4 Transceiver transmit channel

HSMA_TX_N7

1.4-V PCML AA3 Transceiver transmit channel

HSMA_D0

2.5-V AJ29 Dedicated CMOS I/O bit 0

HSMA_D1

2.5-V AK29 Dedicated CMOS I/O bit 1

HSMA_D2

2.5-V AR28 Dedicated CMOS I/O bit 2

HSMA_D3

2.5-V AP28 Dedicated CMOS I/O bit 3

JTAG_TCK

2.5-V — JTAG clock

JTAG_FPGA_TDO_RETIMER

2.5-V — JTAG data input

HSMA_JTAG_TDO

2.5-V — JTAG data output

HSMA_JTAG_TMS

2.5-V — JTAG mode select

Table 2–40. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board

Reference

(J1)

Schematic Signal Name I/O Standard

Stratix V GS

Device Pin

Number

Description

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 73 74

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