Altera Cyclone V E FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 42)

2–34 Chapter 2: Board Components

Memory

Cyclone V E FPGA Development Board March 2013 Altera Corporation

Reference Manual

DDR3_RASN

A24 1.5-V SSTL Class I Row address select

DDR3_RESETN

L19 1.5-V SSTL Class I Reset

DDR3_WEN

B22 1.5-V SSTL Class I Write enable

DDR3_ZQ01

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U7)

DDR3_A0

A16 1.5-V SSTL Class I Address bus

DDR3_A1

G23 1.5-V SSTL Class I Address bus

DDR3_A2

E21 1.5-V SSTL Class I Address bus

DDR3_A3

E22 1.5-V SSTL Class I Address bus

DDR3_A4

A20 1.5-V SSTL Class I Address bus

DDR3_A5

A26 1.5-V SSTL Class I Address bus

DDR3_A6

A15 1.5-V SSTL Class I Address bus

DDR3_A7

B26 1.5-V SSTL Class I Address bus

DDR3_A8

H17 1.5-V SSTL Class I Address bus

DDR3_A9

D14 1.5-V SSTL Class I Address bus

DDR3_A10

E23 1.5-V SSTL Class I Address bus

DDR3_A11

E20 1.5-V SSTL Class I Address bus

DDR3_A12

C25 1.5-V SSTL Class I Address bus

DDR3_A13

B13 1.5-V SSTL Class I Address bus

DDR3_BA0

J18 1.5-V SSTL Class I Bank address bus

DDR3_BA1

F20 1.5-V SSTL Class I Bank address bus

DDR3_BA2

D19 1.5-V SSTL Class I Bank address bus

DDR3_CASN

L20 1.5-V SSTL Class I Row address select

DDR3_CKE

AK18 1.5-V SSTL Class I Column address select

DDR3_CLK_P

J20 1.5-V SSTL Class I Differential output clock

DDR3_CLK_N

H20 1.5-V SSTL Class I Differential output clock

DDR3_CSN

G17 1.5-V SSTL Class I Chip select

DDR3_DM2

A19 1.5-V SSTL Class I Write mask byte lane

DDR3_DM3

B14 1.5-V SSTL Class I Write mask byte lane

DDR3_DQ16

G18 1.5-V SSTL Class I Data bus byte lane 2

DDR3_DQ17

B18 1.5-V SSTL Class I Data bus byte lane 2

DDR3_DQ18

A18 1.5-V SSTL Class I Data bus byte lane 2

DDR3_DQ19

F18 1.5-V SSTL Class I Data bus byte lane 2

DDR3_DQ20

C14 1.5-V SSTL Class I Data bus byte lane 2

DDR3_DQ21

C17 1.5-V SSTL Class I Data bus byte lane 2

DDR3_DQ22

B17 1.5-V SSTL Class I Data bus byte lane 2

DDR3_DQ23

B19 1.5-V SSTL Class I Data bus byte lane 2

DDR3_DQ24

C15 1.5-V SSTL Class I Data bus byte lane 3

Table 2–24. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)

Board

Reference

Schematic

Signal Name

Cyclone V E FPGA

Pin Number

I/O Standard Description

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 55 56

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