Altera Cyclone III LS FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 40)

2–32 Chapter 2: Board Components

Components and Interfaces

Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation

The HSMB data signals 65 through 75, HSMB_D[65:75], are multiplexed with the

LCD data and control signals. The LCD/HSMC port B data select header switch (J18)

controls data multiplexing to the FPGA from the LCD or HSMB_D[65:75]. To control

the HSMB_D[65:75] signals via the FPGA, set LCD_HSMB_SEL to logic 1 by

removing the shunt from the LCD/HSMC port B data select header switch (J18).

Table 2–35 lists the HSMC port B interface pin assignments, signal names, and

functions.

J2.139 LVDS TX bit 14n or CMOS bit 66 HSMA_TX_N14

LVDS or 2.5-V

AE28

J2.140 LVDS RX bit 14n or CMOS bit 67 HSMA_RX_N14 L25

J2.143 LVDS TX bit 15 or CMOS bit 68 HSMA_TX_P15 AF27

J2.144 LVDS RX bit 15 or CMOS bit 69 HSMA_RX_P15 M23

J2.145 LVDS TX bit 15n or CMOS bit 70 HSMA_TX_N15 AE26

J2.146 LVDS RX bit 15n or CMOS bit 71 HSMA_RX_N15 L23

J2.149 LVDS TX bit 16 or CMOS bit 72 HSMA_TX_P16 AD26

J2.150 LVDS RX bit 16 or CMOS bit 73 HSMA_RX_P16 K22

J2.151 LVDS TX bit 16n or CMOS bit 74 HSMA_TX_N16 AD27

J2.152 LVDS RX bit 16n or CMOS bit 75 HSMA_RX_N16 K23

J2.155 LVDS or CMOS clock out 2 or CMOS bit 76 HSMA_CLKOUT_P2 M25

J2.156 LVDS or CMOS clock in 2 or CMOS bit 77 HSMA_CLKIN_P2 T27

J2.157 LVDS or CMOS clock out 2n or CMOS bit 78 HSMA_CLKOUT_N2 N26

J2.158 LVDS or CMOS clock in 2n or CMOS bit 79 HSMA_CLKIN_N2 T28

J2.160 HSMC port A presence detect HSMA_PRSNTn 2.5-V —

Note to Table 2–34:

(1) Board references J2.1 to J2.32 are not connected.

Table 2–34. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3) (1)

Board

Reference Description

Schematic Signal

Name I/O Standard

Cyclone III LS

Device

Pin Number

Table 2–35. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4) (1)

Board

Reference Description

Schematic Signal

Name I/O Standard

Cyclone III LS

Device

Pin Number

J1.33 Management serial data HSMB_SDA

2.5-V

J1.34 Management serial clock HSMB_SCL J5

J1.35 JTAG clock signal JTAG_TCK —

J1.36 JTAG mode select signal JTAG_TMS —

J1.37 JTAG data output HSMB_JTAG_TDO —

J1.38 JTAG data input HSMB_JTAG_TDI —

J1.39 Dedicated CMOS clock out HSMB_CLKOUT0 D2

J1.40 Dedicated CMOS clock in HSMB_CLKIN0 B13

J1.41 Dedicated CMOS I/O bit 0 HSMB_D0 M5

J1.42 Dedicated CMOS I/O bit 1 HSMB_D1 W5

J1.43 Dedicated CMOS I/O bit 2 HSMB_D2 M4

1 2 ... 35 36 37 38 39 40 41 42 43 44 45 ... 57 58

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