Altera Arria V GX FPGA Development Board Manuale Utente Scaricare il pdf (Pagina 68)

2–58 Chapter 2: Board Components

Memory

Arria V GX FPGA Development Board November 2013 Altera Corporation

Reference Manual

Table 2–49 lists the Bull’s Eye connector component reference and manufacturing

information.

Memory

This section describes the development board’s memory interface support and also

their signal names, types, and connectivity relative to the Arria V GX FPGA. The

development board has the following memory interfaces:

■ DDR3

■ QDRII+

■ Flash

f For more information about the memory interfaces, refer to the following documents:

■ Timing Analysis section in volume 4 of the External Memory Interface Handbook.

■ DDR, DDR2, and DDR3 SDRAM Design Tutorials section in volume 6 of the

External Memory Interface Handbook.

DDR3

DDR3A for FPGA 1

The development board supports a 16Mx72x8 bank DDR3 SDRAM interface on

FPGA 1 for very high-speed sequential memory access. The 72-bit data bus consists of

four x16 devices and one x8 device with a single address or command bus. This

interface connects to the vertical I/O banks on the top edge of the FPGA and utilizes

the memory soft controller.

This memory interface is designed to run at a target frequency of 667 MHz for a

maximum theoretical bandwidth of over 115.2 Gbps. The minimum frequency for this

device is 667 MHz. The target Micron device is rated at 800 MHz with a CAS latency

of 11.

Table 2–53. Bull’s Eye Connector Component Reference and Manufacturing Information

Board

Reference

Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

J16

Bull's Eye test point receptacle

Samtec

BAR-J-22

www.samtec.comFour CCA-25M cable assemblies BE25S-01SP1-01.0-02-0152

Insertion/Extraction tool CAT-EX-SCC-01

1 2 ... 63 64 65 66 67 68 69 70 71 72 73 ... 89 90

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Altera Arria V GX FPGA Development Board Manuale Utente Pagina 68