Altera Arria 10 Avalon-MM DMA Manuale Utente Pagina 4
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Data Link Layer Errors ...............................................................................................................................8-2
Transaction Layer Errors ...........................................................................................................................8-3
Error Reporting and Data Poisoning ....................................................................................................... 8-5
Uncorrectable and Correctable Error Status Bits ...................................................................................8-6
IP Core Architecture........................................................................................... 9-1
Top-Level Interfaces ...................................................................................................................................9-3
Avalon-MM DMA Interface.......................................................................................................... 9-3
Clocks and Reset ............................................................................................................................. 9-3
Interrupts ......................................................................................................................................... 9-3
PIPE .................................................................................................................................................. 9-3
Data Link Layer ...........................................................................................................................................9-4
Physical Layer ..............................................................................................................................................9-6
Arria 10 Avalon-MM DMA for PCI Express ..........................................................................................9-8
Design Implementation.................................................................................... 10-1
Making Pin Assignments to Assign I/O Standard to Serial Data Pins ..............................................10-1
Recommended Reset Sequence to Avoid Link Training Issues ......................................................... 10-1
SDC Timing Constraints.......................................................................................................................... 10-2
Frequently Asked Questions.............................................................................. A-1
Additional Information......................................................................................B-1
Revision History for the Avalon-MM Interface with DMA..................................................................B-1
How to Contact Altera................................................................................................................................B-4
Typographic Conventions..........................................................................................................................B-5
TOC-4
Altera Corporation
- PCIe Solutions 1
- Contents 2
- Datasheet 5
- Link Width 6
- ×2 ×4 ×8 6
- Features 6
- Interface 7
- UG-01145_avmm_dma 10
- 2015.05.14 10
- Device Family Support 11
- Related Information 11
- Recommended Speed Grades 12
- Subscribe 14
- <install_dir>/ 14
- Parameter Value 16
- Directory Description 17
- Time TLP Type Payload 17
- TLP Header 17
- Creating a Quartus II Project 18
- Compiling the Design 19
- Parameter Settings 21
- Parameter Value Description 22
- Interface System Settings 25
- Error Reporting 30
- PCIe Address Space Settings 33
- IP Core Interfaces 42
- Reset & 44
- Lock Status 44
- RX Master Module 46
- TX Slave Module 48
- Signal Name Directio 49
- Description 49
- Bits Name Description 51
- Clock Signals 55
- Signal Direction Description 55
- MSI Interrupts for Endpoints 60
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Register Name 91
- Byte Offset 95
- Register Dir Description 95
- Arria 10 Reset and Clocks 100
- Clock Domains 103
- Name Frequency Clock Domain 104
- Error Handling 106
- Data Link Layer Errors 107
- Physical Layer Errors 107
- Error Type Description 107
- Transaction Layer Errors 108
- Status Bit Conditions 111
- Altera Corporation 112
- Send Feedback 112
- IP Core Architecture 113
- Hard IP for PCI Express 114
- Top-Level Interfaces 115
- Data Link Layer 116
- Physical Layer 118
- TX Packets 119
- Altera FPGA 121
- Qsys System 122
- Design Implementation 124
- SDC Timing Constraints 125
- Frequently Asked Questions 126
- Additional Information 127
- Date Version Changes Made 128
- How to Contact Altera 130
- Contact 130
- Contact Method Address 130
- Typographic Conventions 131
- Visual Cue Meaning 131
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