Altera Virtual JTAG IP Core Manuale Utente Pagina 40
- Pagina / 42
- Indice
- SEGNALIBRI
- Introduction 1
- Device Family Support 2
- On-Chip Debugging Tool Suite 2
- JTAG Protocol 4
- JTAG Circuitry Architecture 5
- SLD Hub Finite State Machine 8
- Input Ports 10
- Output Ports 11
- UG-SLDVRTL 12
- 2014.03.19 12
- Parameters 13
- Simulation Model 15
- DescriptionArgumentsCommand 16
- DescriptionSetting 18
- Virtual IR Shift 20
- Virtual DR Shift 20
- Related Information 21
- Simulation Support 25
- CommentsParameter 26
- Altera Corporation 27
- Send Feedback 27
- Compiling the Design 28
- Third-Party Synthesis Support 29
- Binary PatternInstruction 30
- HUB IP Configuration Register 31
- SLD_NODE Info Register 31
- FunctionField 32
- AHDL Function Prototype 33
- VHDL Component Declaration 34
- VHDL LIBRARY-USE Declaration 35
- Write Logic 37
- Read Logic 38
- Runtime Communication 39
- Figure 20: Runtime Execution 40
- Document Revision History 42
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